r9a07g043.dtsi (6f84981772535e670e4e2df051a672af229b6694) r9a07g043.dtsi (85169df721078bf90fb0fc3bf15e4743fea45b2d)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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526 };
527
528 pinctrl: pinctrl@11030000 {
529 compatible = "renesas,r9a07g043-pinctrl";
530 reg = <0 0x11030000 0 0x10000>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pinctrl 0 0 152>;
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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526 };
527
528 pinctrl: pinctrl@11030000 {
529 compatible = "renesas,r9a07g043-pinctrl";
530 reg = <0 0x11030000 0 0x10000>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pinctrl 0 0 152>;
534 #interrupt-cells = <2>;
535 interrupt-controller;
534 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
535 power-domains = <&cpg>;
536 resets = <&cpg R9A07G043_GPIO_RSTN>,
537 <&cpg R9A07G043_GPIO_PORT_RESETN>,
538 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
539 };
540
541 dmac: dma-controller@11820000 {

--- 301 unchanged lines hidden --- 		536 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
537 power-domains = <&cpg>;
538 resets = <&cpg R9A07G043_GPIO_RSTN>,
539 <&cpg R9A07G043_GPIO_PORT_RESETN>,
540 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
541 };
542
543 dmac: dma-controller@11820000 {

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