r9a07g043.dtsi (594ce0b8a998aa4d05827cd7c0d0dcec9a1e3ae2) r9a07g043.dtsi (046084b5e1426efbf08913830bdb101dcbb06be5)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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641 <&cpg R9A07G043_DMAC_RST_ASYNC>;
642 reset-names = "arst", "rst_async";
643 #dma-cells = <1>;
644 dma-channels = <16>;
645 };
646
647 sdhi0: mmc@11c00000 {
648 compatible = "renesas,sdhi-r9a07g043",
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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641 <&cpg R9A07G043_DMAC_RST_ASYNC>;
642 reset-names = "arst", "rst_async";
643 #dma-cells = <1>;
644 dma-channels = <16>;
645 };
646
647 sdhi0: mmc@11c00000 {
648 compatible = "renesas,sdhi-r9a07g043",
649 "renesas,rcar-gen3-sdhi";
649 "renesas,rzg2l-sdhi";
650 reg = <0x0 0x11c00000 0 0x10000>;
651 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
652 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
654 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
655 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
656 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
657 clock-names = "core", "clkh", "cd", "aclk";
658 resets = <&cpg R9A07G043_SDHI0_IXRST>;
659 power-domains = <&cpg>;
660 status = "disabled";
661 };
662
663 sdhi1: mmc@11c10000 {
664 compatible = "renesas,sdhi-r9a07g043",
650 reg = <0x0 0x11c00000 0 0x10000>;
651 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
652 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
654 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
655 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
656 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
657 clock-names = "core", "clkh", "cd", "aclk";
658 resets = <&cpg R9A07G043_SDHI0_IXRST>;
659 power-domains = <&cpg>;
660 status = "disabled";
661 };
662
663 sdhi1: mmc@11c10000 {
664 compatible = "renesas,sdhi-r9a07g043",
665 "renesas,rcar-gen3-sdhi";
665 "renesas,rzg2l-sdhi";
666 reg = <0x0 0x11c10000 0 0x10000>;
667 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
668 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
670 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
671 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
672 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
673 clock-names = "core", "clkh", "cd", "aclk";

--- 239 unchanged lines hidden --- 		666 reg = <0x0 0x11c10000 0 0x10000>;
667 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
668 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
670 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
671 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
672 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
673 clock-names = "core", "clkh", "cd", "aclk";

--- 239 unchanged lines hidden ---