r9a07g043.dtsi (1de1b44833e394e63119fcff37e458a94c244799) r9a07g043.dtsi (e42faad1ef822e186c20e60576b198e1ac9866c4)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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699 };
700
701 wdt2: watchdog@12800400 {
702 reg = <0 0x12800400 0 0x400>;
703 /* place holder */
704 };
705
706 ostm0: timer@12801000 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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699 };
700
701 wdt2: watchdog@12800400 {
702 reg = <0 0x12800400 0 0x400>;
703 /* place holder */
704 };
705
706 ostm0: timer@12801000 {
707 compatible = "renesas,r9a07g043-ostm",
708 "renesas,ostm";
707 reg = <0x0 0x12801000 0x0 0x400>;
709 reg = <0x0 0x12801000 0x0 0x400>;
708 /* place holder */
710 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
711 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
712 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
713 power-domains = <&cpg>;
714 status = "disabled";
709 };
710
711 ostm1: timer@12801400 {
715 };
716
717 ostm1: timer@12801400 {
718 compatible = "renesas,r9a07g043-ostm",
719 "renesas,ostm";
712 reg = <0x0 0x12801400 0x0 0x400>;
720 reg = <0x0 0x12801400 0x0 0x400>;
713 /* place holder */
721 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
722 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
723 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
724 power-domains = <&cpg>;
725 status = "disabled";
714 };
715
716 ostm2: timer@12801800 {
726 };
727
728 ostm2: timer@12801800 {
729 compatible = "renesas,r9a07g043-ostm",
730 "renesas,ostm";
717 reg = <0x0 0x12801800 0x0 0x400>;
731 reg = <0x0 0x12801800 0x0 0x400>;
718 /* place holder */
732 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
733 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
734 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
735 power-domains = <&cpg>;
736 status = "disabled";
719 };
720 };
721
722 timer {
723 compatible = "arm,armv8-timer";
724 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
725 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
726 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
727 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
728 };
729};
737 };
738 };
739
740 timer {
741 compatible = "arm,armv8-timer";
742 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
743 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
744 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
745 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
746 };
747};