r8a77995.dtsi (9ddb236f13594b34a12dacf69a5adca7a1aef35e) r8a77995.dtsi (a2053990f3275e715d69c208d8c0040cac0df593)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8

--- 174 unchanged lines hidden (view full) ---

183 gpio-ranges = <&pfc 0 192 14>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 906>;
187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
188 resets = <&cpg 906>;
189 };
190
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8

--- 174 unchanged lines hidden (view full) ---

183 gpio-ranges = <&pfc 0 192 14>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 906>;
187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
188 resets = <&cpg 906>;
189 };
190
191 pfc: pin-controller@e6060000 {
191 pfc: pinctrl@e6060000 {
192 compatible = "renesas,pfc-r8a77995";
193 reg = <0 0xe6060000 0 0x508>;
194 };
195
196 cpg: clock-controller@e6150000 {
197 compatible = "renesas,r8a77995-cpg-mssr";
198 reg = <0 0xe6150000 0 0x1000>;
199 clocks = <&extal_clk>;

--- 954 unchanged lines hidden --- 		192 compatible = "renesas,pfc-r8a77995";
193 reg = <0 0xe6060000 0 0x508>;
194 };
195
196 cpg: clock-controller@e6150000 {
197 compatible = "renesas,r8a77995-cpg-mssr";
198 reg = <0 0xe6150000 0 0x1000>;
199 clocks = <&extal_clk>;

--- 954 unchanged lines hidden ---