r8a77995.dtsi (5edf8bd6f4a225f7ad0501f921f9717df152e7fb) r8a77995.dtsi (4e4c17c6c3907dfc34051cc450a78a38fb371b4f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8

--- 298 unchanged lines hidden (view full) ---

307 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cpg CPG_MOD 407>;
311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
312 resets = <&cpg 407>;
313 };
314
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8

--- 298 unchanged lines hidden (view full) ---

307 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cpg CPG_MOD 407>;
311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
312 resets = <&cpg 407>;
313 };
314
315 tmu0: timer@e61e0000 {
316 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
317 reg = <0 0xe61e0000 0 0x30>;
318 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&cpg CPG_MOD 125>;
322 clock-names = "fck";
323 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
324 resets = <&cpg 125>;
325 status = "disabled";
326 };
327
328 tmu1: timer@e6fc0000 {
329 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
330 reg = <0 0xe6fc0000 0 0x30>;
331 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cpg CPG_MOD 124>;
335 clock-names = "fck";
336 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
337 resets = <&cpg 124>;
338 status = "disabled";
339 };
340
341 tmu2: timer@e6fd0000 {
342 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
343 reg = <0 0xe6fd0000 0 0x30>;
344 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&cpg CPG_MOD 123>;
348 clock-names = "fck";
349 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
350 resets = <&cpg 123>;
351 status = "disabled";
352 };
353
354 tmu3: timer@e6fe0000 {
355 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
356 reg = <0 0xe6fe0000 0 0x30>;
357 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&cpg CPG_MOD 122>;
361 clock-names = "fck";
362 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
363 resets = <&cpg 122>;
364 status = "disabled";
365 };
366
367 tmu4: timer@ffc00000 {
368 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
369 reg = <0 0xffc00000 0 0x30>;
370 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&cpg CPG_MOD 121>;
374 clock-names = "fck";
375 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
376 resets = <&cpg 121>;
377 status = "disabled";
378 };
379
315 i2c0: i2c@e6500000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "renesas,i2c-r8a77995",
319 "renesas,rcar-gen3-i2c";
320 reg = <0 0xe6500000 0 0x40>;
321 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cpg CPG_MOD 931>;

--- 902 unchanged lines hidden --- 		380 i2c0: i2c@e6500000 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "renesas,i2c-r8a77995",
384 "renesas,rcar-gen3-i2c";
385 reg = <0 0xe6500000 0 0x40>;
386 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cpg CPG_MOD 931>;

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