r8a77990.dtsi (eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1) r8a77990.dtsi (7744b393c95ac470a3ac279fa277e50d947f1bea)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 cluster1_opp: opp_table10 {
58 cluster1_opp: opp-table-1 {
59 compatible = "operating-points-v2";
60 opp-shared;
61 opp-800000000 {
62 opp-hz = /bits/ 64 <800000000>;
63 opp-microvolt = <820000>;
64 clock-latency-ns = <300000>;
65 };
66 opp-1000000000 {

--- 2076 unchanged lines hidden --- 		59 compatible = "operating-points-v2";
60 opp-shared;
61 opp-800000000 {
62 opp-hz = /bits/ 64 <800000000>;
63 opp-microvolt = <820000>;
64 clock-latency-ns = <300000>;
65 };
66 opp-1000000000 {

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