r8a77990.dtsi (bc26b8f4e43acc4d2e3ae0bbf8f20515b4de5c5b) r8a77990.dtsi (de1eb23c6d0f08f6a2eff99afe29b08f023e392d)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>

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22 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0x0>;
24 device_type = "cpu";
25 power-domains = <&sysc 5>;
26 next-level-cache = <&L2_CA53>;
27 enable-method = "psci";
28 };
29
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>

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22 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0x0>;
24 device_type = "cpu";
25 power-domains = <&sysc 5>;
26 next-level-cache = <&L2_CA53>;
27 enable-method = "psci";
28 };
29
30 L2_CA53: cache-controller@0 {
30 L2_CA53: cache-controller-0 {
31 compatible = "cache";
31 compatible = "cache";
32 reg = <0>;
33 power-domains = <&sysc 21>;
34 cache-unified;
35 cache-level = <2>;
36 };
37 };
38
39 extal_clk: extal {
40 compatible = "fixed-clock";

--- 87 unchanged lines hidden --- 		32 power-domains = <&sysc 21>;
33 cache-unified;
34 cache-level = <2>;
35 };
36 };
37
38 extal_clk: extal {
39 compatible = "fixed-clock";

--- 87 unchanged lines hidden ---