r8a77990.dtsi (8fa7d18f9ee2dc20b5ad430e9b0c5336619f05e4) r8a77990.dtsi (70c6d23ea70c19e5166e4e87d9240f8a4d89d8b2)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 74 unchanged lines hidden (view full) ---

83 a53_0: cpu@0 {
84 compatible = "arm,cortex-a53";
85 reg = <0>;
86 device_type = "cpu";
87 #cooling-cells = <2>;
88 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
89 next-level-cache = <&L2_CA53>;
90 enable-method = "psci";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 74 unchanged lines hidden (view full) ---

83 a53_0: cpu@0 {
84 compatible = "arm,cortex-a53";
85 reg = <0>;
86 device_type = "cpu";
87 #cooling-cells = <2>;
88 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
89 next-level-cache = <&L2_CA53>;
90 enable-method = "psci";
91 dynamic-power-coefficient = <277>;
91 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = <&cluster1_opp>;
93 };
94
95 a53_1: cpu@1 {
96 compatible = "arm,cortex-a53";
97 reg = <1>;
98 device_type = "cpu";

--- 1797 unchanged lines hidden --- 		92 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
93 operating-points-v2 = <&cluster1_opp>;
94 };
95
96 a53_1: cpu@1 {
97 compatible = "arm,cortex-a53";
98 reg = <1>;
99 device_type = "cpu";

--- 1797 unchanged lines hidden ---