r8a77990.dtsi (82ffd0454bd9bd57780966d47bfd56d579dd4fb3) r8a77990.dtsi (dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 41 unchanged lines hidden (view full) ---

50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 41 unchanged lines hidden (view full) ---

50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 cluster1_opp: opp_table10 {
59 compatible = "operating-points-v2";
60 opp-shared;
61 opp-800000000 {
62 opp-hz = /bits/ 64 <800000000>;
63 opp-microvolt = <820000>;
64 clock-latency-ns = <300000>;
65 };
66 opp-1000000000 {
67 opp-hz = /bits/ 64 <1000000000>;
68 opp-microvolt = <820000>;
69 clock-latency-ns = <300000>;
70 };
71 opp-1200000000 {
72 opp-hz = /bits/ 64 <1200000000>;
73 opp-microvolt = <820000>;
74 clock-latency-ns = <300000>;
75 opp-suspend;
76 };
77 };
78
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 a53_0: cpu@0 {
63 compatible = "arm,cortex-a53", "arm,armv8";
64 reg = <0>;
65 device_type = "cpu";
66 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
67 next-level-cache = <&L2_CA53>;
68 enable-method = "psci";
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 a53_0: cpu@0 {
84 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <0>;
86 device_type = "cpu";
87 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
88 next-level-cache = <&L2_CA53>;
89 enable-method = "psci";
90 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
91 operating-points-v2 = <&cluster1_opp>;
69 };
70
71 a53_1: cpu@1 {
72 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <1>;
74 device_type = "cpu";
75 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
76 next-level-cache = <&L2_CA53>;
77 enable-method = "psci";
92 };
93
94 a53_1: cpu@1 {
95 compatible = "arm,cortex-a53", "arm,armv8";
96 reg = <1>;
97 device_type = "cpu";
98 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
99 next-level-cache = <&L2_CA53>;
100 enable-method = "psci";
101 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
102 operating-points-v2 = <&cluster1_opp>;
78 };
79
80 L2_CA53: cache-controller-0 {
81 compatible = "cache";
82 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
83 cache-unified;
84 cache-level = <2>;
85 };

--- 149 unchanged lines hidden (view full) ---

235 gpio-ranges = <&pfc 0 192 18>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&cpg CPG_MOD 906>;
239 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
240 resets = <&cpg 906>;
241 };
242
103 };
104
105 L2_CA53: cache-controller-0 {
106 compatible = "cache";
107 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
108 cache-unified;
109 cache-level = <2>;
110 };

--- 149 unchanged lines hidden (view full) ---

260 gpio-ranges = <&pfc 0 192 18>;
261 #interrupt-cells = <2>;
262 interrupt-controller;
263 clocks = <&cpg CPG_MOD 906>;
264 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
265 resets = <&cpg 906>;
266 };
267
268 pfc: pin-controller@e6060000 {
269 compatible = "renesas,pfc-r8a77990";
270 reg = <0 0xe6060000 0 0x508>;
271 };
272
273 i2c_dvfs: i2c@e60b0000 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 compatible = "renesas,iic-r8a77990";
277 reg = <0 0xe60b0000 0 0x15>;
278 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cpg CPG_MOD 926>;
280 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
281 resets = <&cpg 926>;
282 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
283 dma-names = "tx", "rx";
284 status = "disabled";
285 };
286
287 cpg: clock-controller@e6150000 {
288 compatible = "renesas,r8a77990-cpg-mssr";
289 reg = <0 0xe6150000 0 0x1000>;
290 clocks = <&extal_clk>;
291 clock-names = "extal";
292 #clock-cells = <2>;
293 #power-domain-cells = <0>;
294 #reset-cells = <1>;
295 };
296
297 rst: reset-controller@e6160000 {
298 compatible = "renesas,r8a77990-rst";
299 reg = <0 0xe6160000 0 0x0200>;
300 };
301
302 sysc: system-controller@e6180000 {
303 compatible = "renesas,r8a77990-sysc";
304 reg = <0 0xe6180000 0 0x0400>;
305 #power-domain-cells = <1>;
306 };
307
308 thermal: thermal@e6190000 {
309 compatible = "renesas,thermal-r8a77990";
310 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
311 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&cpg CPG_MOD 522>;
315 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
316 resets = <&cpg 522>;
317 #thermal-sensor-cells = <0>;
318 };
319
320 intc_ex: interrupt-controller@e61c0000 {
321 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
322 #interrupt-cells = <2>;
323 interrupt-controller;
324 reg = <0 0xe61c0000 0 0x200>;
325 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cpg CPG_MOD 407>;
332 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
333 resets = <&cpg 407>;
334 };
335
243 i2c0: i2c@e6500000 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "renesas,i2c-r8a77990",
247 "renesas,rcar-gen3-i2c";
248 reg = <0 0xe6500000 0 0x40>;
249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cpg CPG_MOD 931>;

--- 113 unchanged lines hidden (view full) ---

364 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cpg CPG_MOD 1003>;
366 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
367 resets = <&cpg 1003>;
368 i2c-scl-internal-delay-ns = <6>;
369 status = "disabled";
370 };
371
336 i2c0: i2c@e6500000 {
337 #address-cells = <1>;
338 #size-cells = <0>;
339 compatible = "renesas,i2c-r8a77990",
340 "renesas,rcar-gen3-i2c";
341 reg = <0 0xe6500000 0 0x40>;
342 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cpg CPG_MOD 931>;

--- 113 unchanged lines hidden (view full) ---

457 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cpg CPG_MOD 1003>;
459 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
460 resets = <&cpg 1003>;
461 i2c-scl-internal-delay-ns = <6>;
462 status = "disabled";
463 };
464
372 pfc: pin-controller@e6060000 {
373 compatible = "renesas,pfc-r8a77990";
374 reg = <0 0xe6060000 0 0x508>;
375 };
376
377 i2c_dvfs: i2c@e60b0000 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 compatible = "renesas,iic-r8a77990";
381 reg = <0 0xe60b0000 0 0x15>;
382 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cpg CPG_MOD 926>;
384 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
385 resets = <&cpg 926>;
386 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
387 dma-names = "tx", "rx";
388 status = "disabled";
389 };
390
391 cpg: clock-controller@e6150000 {
392 compatible = "renesas,r8a77990-cpg-mssr";
393 reg = <0 0xe6150000 0 0x1000>;
394 clocks = <&extal_clk>;
395 clock-names = "extal";
396 #clock-cells = <2>;
397 #power-domain-cells = <0>;
398 #reset-cells = <1>;
399 };
400
401 rst: reset-controller@e6160000 {
402 compatible = "renesas,r8a77990-rst";
403 reg = <0 0xe6160000 0 0x0200>;
404 };
405
406 sysc: system-controller@e6180000 {
407 compatible = "renesas,r8a77990-sysc";
408 reg = <0 0xe6180000 0 0x0400>;
409 #power-domain-cells = <1>;
410 };
411
412 thermal: thermal@e6190000 {
413 compatible = "renesas,thermal-r8a77990";
414 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
415 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cpg CPG_MOD 522>;
419 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
420 resets = <&cpg 522>;
421 #thermal-sensor-cells = <0>;
422 };
423
424 intc_ex: interrupt-controller@e61c0000 {
425 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
426 #interrupt-cells = <2>;
427 interrupt-controller;
428 reg = <0 0xe61c0000 0 0x200>;
429 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
430 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
433 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&cpg CPG_MOD 407>;
436 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
437 resets = <&cpg 407>;
438 };
439
440 hscif0: serial@e6540000 {
441 compatible = "renesas,hscif-r8a77990",
442 "renesas,rcar-gen3-hscif",
443 "renesas,hscif";
444 reg = <0 0xe6540000 0 0x60>;
445 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cpg CPG_MOD 520>,
447 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,

--- 540 unchanged lines hidden (view full) ---

988 compatible = "renesas,scif-r8a77990",
989 "renesas,rcar-gen3-scif", "renesas,scif";
990 reg = <0 0xe6e88000 0 64>;
991 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&cpg CPG_MOD 310>,
993 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
994 <&scif_clk>;
995 clock-names = "fck", "brg_int", "scif_clk";
465 hscif0: serial@e6540000 {
466 compatible = "renesas,hscif-r8a77990",
467 "renesas,rcar-gen3-hscif",
468 "renesas,hscif";
469 reg = <0 0xe6540000 0 0x60>;
470 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cpg CPG_MOD 520>,
472 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,

--- 540 unchanged lines hidden (view full) ---

1013 compatible = "renesas,scif-r8a77990",
1014 "renesas,rcar-gen3-scif", "renesas,scif";
1015 reg = <0 0xe6e88000 0 64>;
1016 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&cpg CPG_MOD 310>,
1018 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1019 <&scif_clk>;
1020 clock-names = "fck", "brg_int", "scif_clk";
996
1021 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1022 <&dmac2 0x13>, <&dmac2 0x12>;
1023 dma-names = "tx", "rx", "tx", "rx";
997 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
998 resets = <&cpg 310>;
999 status = "disabled";
1000 };
1001
1002 scif3: serial@e6c50000 {
1003 compatible = "renesas,scif-r8a77990",
1004 "renesas,rcar-gen3-scif", "renesas,scif";

--- 516 unchanged lines hidden (view full) ---

1521 interrupts = <GIC_PPI 9
1522 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1523 clocks = <&cpg CPG_MOD 408>;
1524 clock-names = "clk";
1525 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1526 resets = <&cpg 408>;
1527 };
1528
1024 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1025 resets = <&cpg 310>;
1026 status = "disabled";
1027 };
1028
1029 scif3: serial@e6c50000 {
1030 compatible = "renesas,scif-r8a77990",
1031 "renesas,rcar-gen3-scif", "renesas,scif";

--- 516 unchanged lines hidden (view full) ---

1548 interrupts = <GIC_PPI 9
1549 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1550 clocks = <&cpg CPG_MOD 408>;
1551 clock-names = "clk";
1552 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1553 resets = <&cpg 408>;
1554 };
1555
1556 pciec0: pcie@fe000000 {
1557 compatible = "renesas,pcie-r8a77990",
1558 "renesas,pcie-rcar-gen3";
1559 reg = <0 0xfe000000 0 0x80000>;
1560 #address-cells = <3>;
1561 #size-cells = <2>;
1562 bus-range = <0x00 0xff>;
1563 device_type = "pci";
1564 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1565 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1566 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1567 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1568 /* Map all possible DDR as inbound ranges */
1569 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1570 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1573 #interrupt-cells = <1>;
1574 interrupt-map-mask = <0 0 0 0>;
1575 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1577 clock-names = "pcie", "pcie_bus";
1578 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1579 resets = <&cpg 319>;
1580 status = "disabled";
1581 };
1582
1529 vspb0: vsp@fe960000 {
1530 compatible = "renesas,vsp2";
1531 reg = <0 0xfe960000 0 0x8000>;
1532 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&cpg CPG_MOD 626>;
1534 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1535 resets = <&cpg 626>;
1536 renesas,fcp = <&fcpvb0>;

--- 182 unchanged lines hidden (view full) ---

1719 port@1 {
1720 reg = <1>;
1721 lvds1_out: endpoint {
1722 };
1723 };
1724 };
1725 };
1726
1583 vspb0: vsp@fe960000 {
1584 compatible = "renesas,vsp2";
1585 reg = <0 0xfe960000 0 0x8000>;
1586 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MOD 626>;
1588 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1589 resets = <&cpg 626>;
1590 renesas,fcp = <&fcpvb0>;

--- 182 unchanged lines hidden (view full) ---

1773 port@1 {
1774 reg = <1>;
1775 lvds1_out: endpoint {
1776 };
1777 };
1778 };
1779 };
1780
1727 pciec0: pcie@fe000000 {
1728 compatible = "renesas,pcie-r8a77990",
1729 "renesas,pcie-rcar-gen3";
1730 reg = <0 0xfe000000 0 0x80000>;
1731 #address-cells = <3>;
1732 #size-cells = <2>;
1733 bus-range = <0x00 0xff>;
1734 device_type = "pci";
1735 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1736 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1737 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1738 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1739 /* Map all possible DDR as inbound ranges */
1740 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1741 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1744 #interrupt-cells = <1>;
1745 interrupt-map-mask = <0 0 0 0>;
1746 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1747 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1748 clock-names = "pcie", "pcie_bus";
1749 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1750 resets = <&cpg 319>;
1751 status = "disabled";
1752 };
1753
1754 prr: chipid@fff00044 {
1755 compatible = "renesas,prr";
1756 reg = <0 0xfff00044 0 4>;
1757 };
1758 };
1759
1760 thermal-zones {
1761 cpu-thermal {

--- 25 unchanged lines hidden --- 		1781 prr: chipid@fff00044 {
1782 compatible = "renesas,prr";
1783 reg = <0 0xfff00044 0 4>;
1784 };
1785 };
1786
1787 thermal-zones {
1788 cpu-thermal {

--- 25 unchanged lines hidden ---