r8a77990.dtsi (7794bd7ed709abe042fed6e0a09712d8cd55b589) r8a77990.dtsi (8fa7d18f9ee2dc20b5ad430e9b0c5336619f05e4)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 a53_0: cpu@0 {
84 compatible = "arm,cortex-a53";
85 reg = <0>;
86 device_type = "cpu";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 a53_0: cpu@0 {
84 compatible = "arm,cortex-a53";
85 reg = <0>;
86 device_type = "cpu";
87 #cooling-cells = <2>;
87 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
88 next-level-cache = <&L2_CA53>;
89 enable-method = "psci";
90 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
91 operating-points-v2 = <&cluster1_opp>;
92 };
93
94 a53_1: cpu@1 {

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1851 compatible = "renesas,prr";
1852 reg = <0 0xfff00044 0 4>;
1853 };
1854 };
1855
1856 thermal-zones {
1857 cpu-thermal {
1858 polling-delay-passive = <250>;
88 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
89 next-level-cache = <&L2_CA53>;
90 enable-method = "psci";
91 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = <&cluster1_opp>;
93 };
94
95 a53_1: cpu@1 {

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1852 compatible = "renesas,prr";
1853 reg = <0 0xfff00044 0 4>;
1854 };
1855 };
1856
1857 thermal-zones {
1858 cpu-thermal {
1859 polling-delay-passive = <250>;
1859 polling-delay = <1000>;
1860 thermal-sensors = <&thermal>;
1860 polling-delay = <0>;
1861 thermal-sensors = <&thermal 0>;
1862 sustainable-power = <717>;
1861
1862 trips {
1863
1864 trips {
1863 cpu-crit {
1865 target: trip-point1 {
1866 temperature = <100000>;
1867 hysteresis = <2000>;
1868 type = "passive";
1869 };
1870
1871 sensor1_crit: sensor1-crit {
1864 temperature = <120000>;
1865 hysteresis = <2000>;
1866 type = "critical";
1867 };
1868 };
1869
1870 cooling-maps {
1872 temperature = <120000>;
1873 hysteresis = <2000>;
1874 type = "critical";
1875 };
1876 };
1877
1878 cooling-maps {
1879 map0 {
1880 trip = <&target>;
1881 cooling-device = <&a53_0 0 2>;
1882 contribution = <1024>;
1883 };
1871 };
1872 };
1873 };
1874
1875 timer {
1876 compatible = "arm,armv8-timer";
1877 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1878 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1879 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1880 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1881 };
1882};
1884 };
1885 };
1886 };
1887
1888 timer {
1889 compatible = "arm,armv8-timer";
1890 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1891 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1892 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1893 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1894 };
1895};