r8a77990.dtsi (747bbcd3aacd95fe200cdda415dba02e872946b5) r8a77990.dtsi (6af663af3c46300032fd7a783bdc3e585035438f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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1047 };
1048
1049 canfd: can@e66c0000 {
1050 compatible = "renesas,r8a77990-canfd",
1051 "renesas,rcar-gen3-canfd";
1052 reg = <0 0xe66c0000 0 0x8000>;
1053 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

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1047 };
1048
1049 canfd: can@e66c0000 {
1050 compatible = "renesas,r8a77990-canfd",
1051 "renesas,rcar-gen3-canfd";
1052 reg = <0 0xe66c0000 0 0x8000>;
1053 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "ch_int", "g_int";
1055 clocks = <&cpg CPG_MOD 914>,
1056 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1057 <&can_clk>;
1058 clock-names = "fck", "canfd", "can_clk";
1059 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1060 assigned-clock-rates = <40000000>;
1061 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1062 resets = <&cpg 914>;

--- 1103 unchanged lines hidden --- 		1056 clocks = <&cpg CPG_MOD 914>,
1057 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1058 <&can_clk>;
1059 clock-names = "fck", "canfd", "can_clk";
1060 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1061 assigned-clock-rates = <40000000>;
1062 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1063 resets = <&cpg 914>;

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