r8a77990.dtsi (57b54d74dd5c559bd35f2affaf11d8828aaf5733) r8a77990.dtsi (4b03df5fc8c65659e41c3531b627ff615ed8ede9)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "renesas,r8a77990";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "renesas,r8a77990";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 /* 1 core only at this point */
21 a53_0: cpu@0 {
22 compatible = "arm,cortex-a53", "arm,armv8";
20 a53_0: cpu@0 {
21 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0x0>;
22 reg = <0>;
24 device_type = "cpu";
25 power-domains = <&sysc 5>;
26 next-level-cache = <&L2_CA53>;
27 enable-method = "psci";
28 };
29
23 device_type = "cpu";
24 power-domains = <&sysc 5>;
25 next-level-cache = <&L2_CA53>;
26 enable-method = "psci";
27 };
28
29 a53_1: cpu@1 {
30 compatible = "arm,cortex-a53", "arm,armv8";
31 reg = <1>;
32 device_type = "cpu";
33 power-domains = <&sysc 6>;
34 next-level-cache = <&L2_CA53>;
35 enable-method = "psci";
36 };
37
30 L2_CA53: cache-controller-0 {
31 compatible = "cache";
32 power-domains = <&sysc 21>;
33 cache-unified;
34 cache-level = <2>;
35 };
36 };
37
38 extal_clk: extal {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridden by the board */
42 clock-frequency = <0>;
43 };
44
45 pmu_a53 {
46 compatible = "arm,cortex-a53-pmu";
38 L2_CA53: cache-controller-0 {
39 compatible = "cache";
40 power-domains = <&sysc 21>;
41 cache-unified;
42 cache-level = <2>;
43 };
44 };
45
46 extal_clk: extal {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 /* This value must be overridden by the board */
50 clock-frequency = <0>;
51 };
52
53 pmu_a53 {
54 compatible = "arm,cortex-a53-pmu";
47 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&a53_0>;
55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
56 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-affinity = <&a53_0>, <&a53_1>;
49 };
50
51 psci {
52 compatible = "arm,psci-1.0", "arm,psci-0.2";
53 method = "smc";
54 };
55
56 soc: soc {
57 compatible = "simple-bus";
58 interrupt-parent = <&gic>;
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
58 };
59
60 psci {
61 compatible = "arm,psci-1.0", "arm,psci-0.2";
62 method = "smc";
63 };
64
65 soc: soc {
66 compatible = "simple-bus";
67 interrupt-parent = <&gic>;
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
72 rwdt: watchdog@e6020000 {
73 compatible = "renesas,r8a77990-wdt",
74 "renesas,rcar-gen3-wdt";
75 reg = <0 0xe6020000 0 0x0c>;
76 clocks = <&cpg CPG_MOD 402>;
77 power-domains = <&sysc 32>;
78 resets = <&cpg 402>;
79 status = "disabled";
80 };
81
63 gpio0: gpio@e6050000 {
64 compatible = "renesas,gpio-r8a77990",
65 "renesas,rcar-gen3-gpio";
66 reg = <0 0xe6050000 0 0x50>;
67 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
68 #gpio-cells = <2>;
69 gpio-controller;
70 gpio-ranges = <&pfc 0 0 18>;

--- 118 unchanged lines hidden (view full) ---

189 compatible = "renesas,r8a77990-sysc";
190 reg = <0 0xe6180000 0 0x0400>;
191 #power-domain-cells = <1>;
192 };
193
194 avb: ethernet@e6800000 {
195 compatible = "renesas,etheravb-r8a77990",
196 "renesas,etheravb-rcar-gen3";
82 gpio0: gpio@e6050000 {
83 compatible = "renesas,gpio-r8a77990",
84 "renesas,rcar-gen3-gpio";
85 reg = <0 0xe6050000 0 0x50>;
86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
87 #gpio-cells = <2>;
88 gpio-controller;
89 gpio-ranges = <&pfc 0 0 18>;

--- 118 unchanged lines hidden (view full) ---

208 compatible = "renesas,r8a77990-sysc";
209 reg = <0 0xe6180000 0 0x0400>;
210 #power-domain-cells = <1>;
211 };
212
213 avb: ethernet@e6800000 {
214 compatible = "renesas,etheravb-r8a77990",
215 "renesas,etheravb-rcar-gen3";
197 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
216 reg = <0 0xe6800000 0 0x800>;
198 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

--- 37 unchanged lines hidden (view full) ---

243 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg CPG_MOD 310>;
245 clock-names = "fck";
246 power-domains = <&sysc 32>;
247 resets = <&cpg 310>;
248 status = "disabled";
249 };
250
217 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

--- 37 unchanged lines hidden (view full) ---

262 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&cpg CPG_MOD 310>;
264 clock-names = "fck";
265 power-domains = <&sysc 32>;
266 resets = <&cpg 310>;
267 status = "disabled";
268 };
269
270 ohci0: usb@ee080000 {
271 compatible = "generic-ohci";
272 reg = <0 0xee080000 0 0x100>;
273 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&cpg CPG_MOD 703>;
275 phys = <&usb2_phy0>;
276 phy-names = "usb";
277 power-domains = <&sysc 32>;
278 resets = <&cpg 703>;
279 status = "disabled";
280 };
281
282 ehci0: usb@ee080100 {
283 compatible = "generic-ehci";
284 reg = <0 0xee080100 0 0x100>;
285 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cpg CPG_MOD 703>;
287 phys = <&usb2_phy0>;
288 phy-names = "usb";
289 companion = <&ohci0>;
290 power-domains = <&sysc 32>;
291 resets = <&cpg 703>;
292 status = "disabled";
293 };
294
295 usb2_phy0: usb-phy@ee080200 {
296 compatible = "renesas,usb2-phy-r8a77990",
297 "renesas,rcar-gen3-usb2-phy";
298 reg = <0 0xee080200 0 0x700>;
299 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cpg CPG_MOD 703>;
301 power-domains = <&sysc 32>;
302 resets = <&cpg 703>;
303 #phy-cells = <0>;
304 status = "disabled";
305 };
306
251 gic: interrupt-controller@f1010000 {
252 compatible = "arm,gic-400";
253 #interrupt-cells = <3>;
254 #address-cells = <0>;
255 interrupt-controller;
256 reg = <0x0 0xf1010000 0 0x1000>,
257 <0x0 0xf1020000 0 0x20000>,
258 <0x0 0xf1040000 0 0x20000>,
259 <0x0 0xf1060000 0 0x20000>;
260 interrupts = <GIC_PPI 9
307 gic: interrupt-controller@f1010000 {
308 compatible = "arm,gic-400";
309 #interrupt-cells = <3>;
310 #address-cells = <0>;
311 interrupt-controller;
312 reg = <0x0 0xf1010000 0 0x1000>,
313 <0x0 0xf1020000 0 0x20000>,
314 <0x0 0xf1040000 0 0x20000>,
315 <0x0 0xf1060000 0 0x20000>;
316 interrupts = <GIC_PPI 9
261 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
317 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
262 clocks = <&cpg CPG_MOD 408>;
263 clock-names = "clk";
264 power-domains = <&sysc 32>;
265 resets = <&cpg 408>;
266 };
267
268 prr: chipid@fff00044 {
269 compatible = "renesas,prr";
270 reg = <0 0xfff00044 0 4>;
271 };
272 };
273
274 timer {
275 compatible = "arm,armv8-timer";
318 clocks = <&cpg CPG_MOD 408>;
319 clock-names = "clk";
320 power-domains = <&sysc 32>;
321 resets = <&cpg 408>;
322 };
323
324 prr: chipid@fff00044 {
325 compatible = "renesas,prr";
326 reg = <0 0xfff00044 0 4>;
327 };
328 };
329
330 timer {
331 compatible = "arm,armv8-timer";
276 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
277 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
278 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
279 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
332 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
333 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
334 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
335 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
280 };
281};
336 };
337};