r8a77990.dtsi (4b7e3ab1916931dee402bd50a764c694df6f6a1c) r8a77990.dtsi (ec70407ae7d790d6b34bfe582901c1149e842248)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 467 unchanged lines hidden (view full) ---

476 clocks = <&cpg CPG_MOD 208>;
477 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
478 resets = <&cpg 208>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
483
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

--- 467 unchanged lines hidden (view full) ---

476 clocks = <&cpg CPG_MOD 208>;
477 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
478 resets = <&cpg 208>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
483
484 vin4: video@e6ef4000 {
485 compatible = "renesas,vin-r8a77990";
486 reg = <0 0xe6ef4000 0 0x1000>;
487 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cpg CPG_MOD 807>;
489 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
490 resets = <&cpg 807>;
491 renesas,id = <4>;
492 status = "disabled";
493
494 ports {
495 #address-cells = <1>;
496 #size-cells = <0>;
497
498 port@1 {
499 reg = <1>;
500
501 vin4csi40: endpoint {
502 remote-endpoint= <&csi40vin4>;
503 };
504 };
505 };
506 };
507
508 vin5: video@e6ef5000 {
509 compatible = "renesas,vin-r8a77990";
510 reg = <0 0xe6ef5000 0 0x1000>;
511 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cpg CPG_MOD 806>;
513 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
514 resets = <&cpg 806>;
515 renesas,id = <5>;
516 status = "disabled";
517
518 ports {
519 #address-cells = <1>;
520 #size-cells = <0>;
521
522 port@1 {
523 reg = <1>;
524
525 vin5csi40: endpoint {
526 remote-endpoint= <&csi40vin5>;
527 };
528 };
529 };
530 };
531
484 xhci0: usb@ee000000 {
485 compatible = "renesas,xhci-r8a77990",
486 "renesas,rcar-gen3-xhci";
487 reg = <0 0xee000000 0 0xc00>;
488 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cpg CPG_MOD 328>;
490 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
491 resets = <&cpg 328>;

--- 49 unchanged lines hidden (view full) ---

541 interrupts = <GIC_PPI 9
542 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
543 clocks = <&cpg CPG_MOD 408>;
544 clock-names = "clk";
545 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
546 resets = <&cpg 408>;
547 };
548
532 xhci0: usb@ee000000 {
533 compatible = "renesas,xhci-r8a77990",
534 "renesas,rcar-gen3-xhci";
535 reg = <0 0xee000000 0 0xc00>;
536 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cpg CPG_MOD 328>;
538 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
539 resets = <&cpg 328>;

--- 49 unchanged lines hidden (view full) ---

589 interrupts = <GIC_PPI 9
590 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
591 clocks = <&cpg CPG_MOD 408>;
592 clock-names = "clk";
593 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
594 resets = <&cpg 408>;
595 };
596
597 csi40: csi2@feaa0000 {
598 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
599 reg = <0 0xfeaa0000 0 0x10000>;
600 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cpg CPG_MOD 716>;
602 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
603 resets = <&cpg 716>;
604 status = "disabled";
605
606 ports {
607 #address-cells = <1>;
608 #size-cells = <0>;
609
610 port@1 {
611 #address-cells = <1>;
612 #size-cells = <0>;
613
614 reg = <1>;
615
616 csi40vin4: endpoint@0 {
617 reg = <0>;
618 remote-endpoint = <&vin4csi40>;
619 };
620 csi40vin5: endpoint@1 {
621 reg = <1>;
622 remote-endpoint = <&vin5csi40>;
623 };
624 };
625 };
626 };
627
549 prr: chipid@fff00044 {
550 compatible = "renesas,prr";
551 reg = <0 0xfff00044 0 4>;
552 };
553 };
554
555 timer {
556 compatible = "arm,armv8-timer";
557 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
558 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
559 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
560 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
561 };
562};
628 prr: chipid@fff00044 {
629 compatible = "renesas,prr";
630 reg = <0 0xfff00044 0 4>;
631 };
632 };
633
634 timer {
635 compatible = "arm,armv8-timer";
636 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
637 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
638 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
639 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
640 };
641};