r8a77990.dtsi (4ab0df3399699c3d440940863234d318fa649b72) | r8a77990.dtsi (0d292de1ebe0cfc599d7eeccdff4aa0d77a03f55) |
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1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the r8a77990 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> --- 46 unchanged lines hidden (view full) --- 55 56 soc: soc { 57 compatible = "simple-bus"; 58 interrupt-parent = <&gic>; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the r8a77990 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> --- 46 unchanged lines hidden (view full) --- 55 56 soc: soc { 57 compatible = "simple-bus"; 58 interrupt-parent = <&gic>; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 |
63 gpio0: gpio@e6050000 { 64 compatible = "renesas,gpio-r8a77990", 65 "renesas,rcar-gen3-gpio"; 66 reg = <0 0xe6050000 0 0x50>; 67 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 68 #gpio-cells = <2>; 69 gpio-controller; 70 gpio-ranges = <&pfc 0 0 18>; 71 #interrupt-cells = <2>; 72 interrupt-controller; 73 clocks = <&cpg CPG_MOD 912>; 74 power-domains = <&sysc 32>; 75 resets = <&cpg 912>; 76 }; 77 78 gpio1: gpio@e6051000 { 79 compatible = "renesas,gpio-r8a77990", 80 "renesas,rcar-gen3-gpio"; 81 reg = <0 0xe6051000 0 0x50>; 82 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 83 #gpio-cells = <2>; 84 gpio-controller; 85 gpio-ranges = <&pfc 0 32 23>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 clocks = <&cpg CPG_MOD 911>; 89 power-domains = <&sysc 32>; 90 resets = <&cpg 911>; 91 }; 92 93 gpio2: gpio@e6052000 { 94 compatible = "renesas,gpio-r8a77990", 95 "renesas,rcar-gen3-gpio"; 96 reg = <0 0xe6052000 0 0x50>; 97 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 98 #gpio-cells = <2>; 99 gpio-controller; 100 gpio-ranges = <&pfc 0 64 26>; 101 #interrupt-cells = <2>; 102 interrupt-controller; 103 clocks = <&cpg CPG_MOD 910>; 104 power-domains = <&sysc 32>; 105 resets = <&cpg 910>; 106 }; 107 108 gpio3: gpio@e6053000 { 109 compatible = "renesas,gpio-r8a77990", 110 "renesas,rcar-gen3-gpio"; 111 reg = <0 0xe6053000 0 0x50>; 112 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 113 #gpio-cells = <2>; 114 gpio-controller; 115 gpio-ranges = <&pfc 0 96 16>; 116 #interrupt-cells = <2>; 117 interrupt-controller; 118 clocks = <&cpg CPG_MOD 909>; 119 power-domains = <&sysc 32>; 120 resets = <&cpg 909>; 121 }; 122 123 gpio4: gpio@e6054000 { 124 compatible = "renesas,gpio-r8a77990", 125 "renesas,rcar-gen3-gpio"; 126 reg = <0 0xe6054000 0 0x50>; 127 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 128 #gpio-cells = <2>; 129 gpio-controller; 130 gpio-ranges = <&pfc 0 128 11>; 131 #interrupt-cells = <2>; 132 interrupt-controller; 133 clocks = <&cpg CPG_MOD 908>; 134 power-domains = <&sysc 32>; 135 resets = <&cpg 908>; 136 }; 137 138 gpio5: gpio@e6055000 { 139 compatible = "renesas,gpio-r8a77990", 140 "renesas,rcar-gen3-gpio"; 141 reg = <0 0xe6055000 0 0x50>; 142 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 143 #gpio-cells = <2>; 144 gpio-controller; 145 gpio-ranges = <&pfc 0 160 20>; 146 #interrupt-cells = <2>; 147 interrupt-controller; 148 clocks = <&cpg CPG_MOD 907>; 149 power-domains = <&sysc 32>; 150 resets = <&cpg 907>; 151 }; 152 153 gpio6: gpio@e6055400 { 154 compatible = "renesas,gpio-r8a77990", 155 "renesas,rcar-gen3-gpio"; 156 reg = <0 0xe6055400 0 0x50>; 157 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 158 #gpio-cells = <2>; 159 gpio-controller; 160 gpio-ranges = <&pfc 0 192 18>; 161 #interrupt-cells = <2>; 162 interrupt-controller; 163 clocks = <&cpg CPG_MOD 906>; 164 power-domains = <&sysc 32>; 165 resets = <&cpg 906>; 166 }; 167 |
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63 pfc: pin-controller@e6060000 { 64 compatible = "renesas,pfc-r8a77990"; 65 reg = <0 0xe6060000 0 0x508>; 66 }; 67 68 cpg: clock-controller@e6150000 { 69 compatible = "renesas,r8a77990-cpg-mssr"; 70 reg = <0 0xe6150000 0 0x1000>; --- 61 unchanged lines hidden --- | 168 pfc: pin-controller@e6060000 { 169 compatible = "renesas,pfc-r8a77990"; 170 reg = <0 0xe6060000 0 0x508>; 171 }; 172 173 cpg: clock-controller@e6150000 { 174 compatible = "renesas,r8a77990-cpg-mssr"; 175 reg = <0 0xe6150000 0 0x1000>; --- 61 unchanged lines hidden --- |