r8a77990.dtsi (26af34079f1d8299932303cfd2b376b9cf55a35c) r8a77990.dtsi (28a5c61b5136d58325e2a9504f4673d514ebf2e8)
1/* SPDX-License-Identifier: GPL-2.0 */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a77990-sysc.h>
11
12/ {
13 compatible = "renesas,r8a77990";

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279 clocks = <&cpg CPG_MOD 926>;
280 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
281 resets = <&cpg 926>;
282 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
283 dma-names = "tx", "rx";
284 status = "disabled";
285 };
286
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a77990-sysc.h>
11
12/ {
13 compatible = "renesas,r8a77990";

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279 clocks = <&cpg CPG_MOD 926>;
280 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
281 resets = <&cpg 926>;
282 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
283 dma-names = "tx", "rx";
284 status = "disabled";
285 };
286
287 cmt0: timer@e60f0000 {
288 compatible = "renesas,r8a77990-cmt0",
289 "renesas,rcar-gen3-cmt0";
290 reg = <0 0xe60f0000 0 0x1004>;
291 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&cpg CPG_MOD 303>;
294 clock-names = "fck";
295 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
296 resets = <&cpg 303>;
297 status = "disabled";
298 };
299
300 cmt1: timer@e6130000 {
301 compatible = "renesas,r8a77990-cmt1",
302 "renesas,rcar-gen3-cmt1";
303 reg = <0 0xe6130000 0 0x1004>;
304 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cpg CPG_MOD 302>;
313 clock-names = "fck";
314 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
315 resets = <&cpg 302>;
316 status = "disabled";
317 };
318
319 cmt2: timer@e6140000 {
320 compatible = "renesas,r8a77990-cmt1",
321 "renesas,rcar-gen3-cmt1";
322 reg = <0 0xe6140000 0 0x1004>;
323 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cpg CPG_MOD 301>;
332 clock-names = "fck";
333 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
334 resets = <&cpg 301>;
335 status = "disabled";
336 };
337
338 cmt3: timer@e6148000 {
339 compatible = "renesas,r8a77990-cmt1",
340 "renesas,rcar-gen3-cmt1";
341 reg = <0 0xe6148000 0 0x1004>;
342 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cpg CPG_MOD 300>;
351 clock-names = "fck";
352 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
353 resets = <&cpg 300>;
354 status = "disabled";
355 };
356
287 cpg: clock-controller@e6150000 {
288 compatible = "renesas,r8a77990-cpg-mssr";
289 reg = <0 0xe6150000 0 0x1000>;
290 clocks = <&extal_clk>;
291 clock-names = "extal";
292 #clock-cells = <2>;
293 #power-domain-cells = <0>;
294 #reset-cells = <1>;

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1062 compatible = "renesas,scif-r8a77990",
1063 "renesas,rcar-gen3-scif", "renesas,scif";
1064 reg = <0 0xe6f30000 0 64>;
1065 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&cpg CPG_MOD 202>,
1067 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1068 <&scif_clk>;
1069 clock-names = "fck", "brg_int", "scif_clk";
357 cpg: clock-controller@e6150000 {
358 compatible = "renesas,r8a77990-cpg-mssr";
359 reg = <0 0xe6150000 0 0x1000>;
360 clocks = <&extal_clk>;
361 clock-names = "extal";
362 #clock-cells = <2>;
363 #power-domain-cells = <0>;
364 #reset-cells = <1>;

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1132 compatible = "renesas,scif-r8a77990",
1133 "renesas,rcar-gen3-scif", "renesas,scif";
1134 reg = <0 0xe6f30000 0 64>;
1135 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&cpg CPG_MOD 202>,
1137 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1138 <&scif_clk>;
1139 clock-names = "fck", "brg_int", "scif_clk";
1070 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1071 dma-names = "tx", "rx";
1140 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1141 <&dmac2 0x5b>, <&dmac2 0x5a>;
1142 dma-names = "tx", "rx", "tx", "rx";
1072 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 202>;
1074 status = "disabled";
1075 };
1076
1077 msiof0: spi@e6e90000 {
1078 compatible = "renesas,msiof-r8a77990",
1079 "renesas,rcar-gen3-msiof";

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1651 reg = <0 0xfea2f000 0 0x200>;
1652 clocks = <&cpg CPG_MOD 602>;
1653 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1654 resets = <&cpg 602>;
1655 iommus = <&ipmmu_vi0 9>;
1656 };
1657
1658 csi40: csi2@feaa0000 {
1143 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1144 resets = <&cpg 202>;
1145 status = "disabled";
1146 };
1147
1148 msiof0: spi@e6e90000 {
1149 compatible = "renesas,msiof-r8a77990",
1150 "renesas,rcar-gen3-msiof";

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1722 reg = <0 0xfea2f000 0 0x200>;
1723 clocks = <&cpg CPG_MOD 602>;
1724 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1725 resets = <&cpg 602>;
1726 iommus = <&ipmmu_vi0 9>;
1727 };
1728
1729 csi40: csi2@feaa0000 {
1659 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
1730 compatible = "renesas,r8a77990-csi2";
1660 reg = <0 0xfeaa0000 0 0x10000>;
1661 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MOD 716>;
1663 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1664 resets = <&cpg 716>;
1665 status = "disabled";
1666
1667 ports {

--- 145 unchanged lines hidden --- 		1731 reg = <0 0xfeaa0000 0 0x10000>;
1732 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1733 clocks = <&cpg CPG_MOD 716>;
1734 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1735 resets = <&cpg 716>;
1736 status = "disabled";
1737
1738 ports {

--- 145 unchanged lines hidden ---