r8a77980.dtsi (efcb52e35d162dc9104be56492b65049a17dc6a4) r8a77980.dtsi (a334e781e01afeb97634480ec0d9819287b79a68)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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648 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
649 IRQ_TYPE_LEVEL_HIGH)>;
650 clocks = <&cpg CPG_MOD 408>;
651 clock-names = "clk";
652 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
653 resets = <&cpg 408>;
654 };
655
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

--- 639 unchanged lines hidden (view full) ---

648 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
649 IRQ_TYPE_LEVEL_HIGH)>;
650 clocks = <&cpg CPG_MOD 408>;
651 clock-names = "clk";
652 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
653 resets = <&cpg 408>;
654 };
655
656 vspd0: vsp@fea20000 {
657 compatible = "renesas,vsp2";
658 reg = <0 0xfea20000 0 0x5000>;
659 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&cpg CPG_MOD 623>;
661 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
662 resets = <&cpg 623>;
663 renesas,fcp = <&fcpvd0>;
664 };
665
666 fcpvd0: fcp@fea27000 {
667 compatible = "renesas,fcpv";
668 reg = <0 0xfea27000 0 0x200>;
669 clocks = <&cpg CPG_MOD 603>;
670 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
671 resets = <&cpg 603>;
672 };
673
674 du: display@feb00000 {
675 compatible = "renesas,du-r8a77980",
676 "renesas,du-r8a77970";
677 reg = <0 0xfeb00000 0 0x80000>;
678 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&cpg CPG_MOD 724>;
680 clock-names = "du.0";
681 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
682 resets = <&cpg 724>;
683 vsps = <&vspd0>;
684 status = "disabled";
685
686 ports {
687 #address-cells = <1>;
688 #size-cells = <0>;
689
690 port@0 {
691 reg = <0>;
692 du_out_rgb: endpoint {
693 };
694 };
695
696 port@1 {
697 reg = <1>;
698 du_out_lvds0: endpoint {
699 remote-endpoint = <&lvds0_in>;
700 };
701 };
702 };
703 };
704
705 lvds0: lvds-encoder@feb90000 {
706 compatible = "renesas,r8a77980-lvds";
707 reg = <0 0xfeb90000 0 0x14>;
708 clocks = <&cpg CPG_MOD 727>;
709 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
710 resets = <&cpg 727>;
711 status = "disabled";
712
713 ports {
714 #address-cells = <1>;
715 #size-cells = <0>;
716
717 port@0 {
718 reg = <0>;
719 lvds0_in: endpoint {
720 remote-endpoint =
721 <&du_out_lvds0>;
722 };
723 };
724
725 port@1 {
726 reg = <1>;
727 lvds0_out: endpoint {
728 };
729 };
730 };
731 };
732
656 prr: chipid@fff00044 {
657 compatible = "renesas,prr";
658 reg = <0 0xfff00044 0 4>;
659 };
660 };
661
662 timer {
663 compatible = "arm,armv8-timer";
664 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
665 IRQ_TYPE_LEVEL_LOW)>,
666 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
667 IRQ_TYPE_LEVEL_LOW)>,
668 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
669 IRQ_TYPE_LEVEL_LOW)>,
670 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
671 IRQ_TYPE_LEVEL_LOW)>;
672 };
673};
733 prr: chipid@fff00044 {
734 compatible = "renesas,prr";
735 reg = <0 0xfff00044 0 4>;
736 };
737 };
738
739 timer {
740 compatible = "arm,armv8-timer";
741 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
742 IRQ_TYPE_LEVEL_LOW)>,
743 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
744 IRQ_TYPE_LEVEL_LOW)>,
745 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
746 IRQ_TYPE_LEVEL_LOW)>,
747 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
748 IRQ_TYPE_LEVEL_LOW)>;
749 };
750};