r8a77980.dtsi (cef26946f247c75a3b1c7919ea801d2ea8511f00) r8a77980.dtsi (63eb8ee5333657677789ba3454dd5b86fc53311b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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348 clocks = <&cpg CPG_MOD 217>;
349 clock-names = "fck";
350 power-domains = <&sysc 32>;
351 resets = <&cpg 217>;
352 #dma-cells = <1>;
353 dma-channels = <16>;
354 };
355
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

--- 339 unchanged lines hidden (view full) ---

348 clocks = <&cpg CPG_MOD 217>;
349 clock-names = "fck";
350 power-domains = <&sysc 32>;
351 resets = <&cpg 217>;
352 #dma-cells = <1>;
353 dma-channels = <16>;
354 };
355
356 mmc0: mmc@ee140000 {
357 compatible = "renesas,sdhi-r8a77980",
358 "renesas,rcar-gen3-sdhi";
359 reg = <0 0xee140000 0 0x2000>;
360 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cpg CPG_MOD 314>;
362 power-domains = <&sysc 32>;
363 resets = <&cpg 314>;
364 max-frequency = <200000000>;
365 status = "disabled";
366 };
367
356 gic: interrupt-controller@f1010000 {
357 compatible = "arm,gic-400";
358 #interrupt-cells = <3>;
359 #address-cells = <0>;
360 interrupt-controller;
361 reg = <0x0 0xf1010000 0 0x1000>,
362 <0x0 0xf1020000 0 0x20000>,
363 <0x0 0xf1040000 0 0x20000>,

--- 27 unchanged lines hidden --- 		368 gic: interrupt-controller@f1010000 {
369 compatible = "arm,gic-400";
370 #interrupt-cells = <3>;
371 #address-cells = <0>;
372 interrupt-controller;
373 reg = <0x0 0xf1010000 0 0x1000>,
374 <0x0 0xf1020000 0 0x20000>,
375 <0x0 0xf1040000 0 0x20000>,

--- 27 unchanged lines hidden ---