r8a77980.dtsi (bba9525520b6028ecbe7486e13216e9ede8636be) r8a77980.dtsi (cef26946f247c75a3b1c7919ea801d2ea8511f00)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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66 soc {
67 compatible = "simple-bus";
68 interrupt-parent = <&gic>;
69
70 #address-cells = <2>;
71 #size-cells = <2>;
72 ranges;
73
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

--- 57 unchanged lines hidden (view full) ---

66 soc {
67 compatible = "simple-bus";
68 interrupt-parent = <&gic>;
69
70 #address-cells = <2>;
71 #size-cells = <2>;
72 ranges;
73
74 pfc: pin-controller@e6060000 {
75 compatible = "renesas,pfc-r8a77980";
76 reg = <0 0xe6060000 0 0x50c>;
77 };
78
74 cpg: clock-controller@e6150000 {
75 compatible = "renesas,r8a77980-cpg-mssr";
76 reg = <0 0xe6150000 0 0x1000>;
77 clocks = <&extal_clk>, <&extalr_clk>;
78 clock-names = "extal", "extalr";
79 #clock-cells = <2>;
80 #power-domain-cells = <0>;
81 #reset-cells = <1>;

--- 304 unchanged lines hidden --- 		79 cpg: clock-controller@e6150000 {
80 compatible = "renesas,r8a77980-cpg-mssr";
81 reg = <0 0xe6150000 0 0x1000>;
82 clocks = <&extal_clk>, <&extalr_clk>;
83 clock-names = "extal", "extalr";
84 #clock-cells = <2>;
85 #power-domain-cells = <0>;
86 #reset-cells = <1>;

--- 304 unchanged lines hidden ---