r8a77980.dtsi (7731b8bc94e599c9a79e428f3359ff2c34b7576a) r8a77980.dtsi (2ec1e4b4a815ee872fb29753f4872abf1a2e62a4)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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25 compatible = "arm,cortex-a53", "arm,armv8";
26 reg = <0>;
27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
29 next-level-cache = <&L2_CA53>;
30 enable-method = "psci";
31 };
32
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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25 compatible = "arm,cortex-a53", "arm,armv8";
26 reg = <0>;
27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
29 next-level-cache = <&L2_CA53>;
30 enable-method = "psci";
31 };
32
33 a53_1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <1>;
37 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
38 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
39 next-level-cache = <&L2_CA53>;
40 enable-method = "psci";
41 };
42
43 a53_2: cpu@2 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a53", "arm,armv8";
46 reg = <2>;
47 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
48 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
49 next-level-cache = <&L2_CA53>;
50 enable-method = "psci";
51 };
52
53 a53_3: cpu@3 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53", "arm,armv8";
56 reg = <3>;
57 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
58 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
59 next-level-cache = <&L2_CA53>;
60 enable-method = "psci";
61 };
62
33 L2_CA53: cache-controller {
34 compatible = "cache";
35 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
36 cache-unified;
37 cache-level = <2>;
38 };
39 };
40

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403 compatible = "arm,gic-400";
404 #interrupt-cells = <3>;
405 #address-cells = <0>;
406 interrupt-controller;
407 reg = <0x0 0xf1010000 0 0x1000>,
408 <0x0 0xf1020000 0 0x20000>,
409 <0x0 0xf1040000 0 0x20000>,
410 <0x0 0xf1060000 0 0x20000>;
63 L2_CA53: cache-controller {
64 compatible = "cache";
65 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
66 cache-unified;
67 cache-level = <2>;
68 };
69 };
70

--- 362 unchanged lines hidden (view full) ---

433 compatible = "arm,gic-400";
434 #interrupt-cells = <3>;
435 #address-cells = <0>;
436 interrupt-controller;
437 reg = <0x0 0xf1010000 0 0x1000>,
438 <0x0 0xf1020000 0 0x20000>,
439 <0x0 0xf1040000 0 0x20000>,
440 <0x0 0xf1060000 0 0x20000>;
411 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
441 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
412 IRQ_TYPE_LEVEL_HIGH)>;
413 clocks = <&cpg CPG_MOD 408>;
414 clock-names = "clk";
415 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
416 resets = <&cpg 408>;
417 };
418
419 prr: chipid@fff00044 {
420 compatible = "renesas,prr";
421 reg = <0 0xfff00044 0 4>;
422 };
423 };
424
425 timer {
426 compatible = "arm,armv8-timer";
442 IRQ_TYPE_LEVEL_HIGH)>;
443 clocks = <&cpg CPG_MOD 408>;
444 clock-names = "clk";
445 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
446 resets = <&cpg 408>;
447 };
448
449 prr: chipid@fff00044 {
450 compatible = "renesas,prr";
451 reg = <0 0xfff00044 0 4>;
452 };
453 };
454
455 timer {
456 compatible = "arm,armv8-timer";
427 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
457 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
428 IRQ_TYPE_LEVEL_LOW)>,
458 IRQ_TYPE_LEVEL_LOW)>,
429 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
459 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
430 IRQ_TYPE_LEVEL_LOW)>,
460 IRQ_TYPE_LEVEL_LOW)>,
431 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
461 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
432 IRQ_TYPE_LEVEL_LOW)>,
462 IRQ_TYPE_LEVEL_LOW)>,
433 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
463 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
434 IRQ_TYPE_LEVEL_LOW)>;
435 };
436};
464 IRQ_TYPE_LEVEL_LOW)>;
465 };
466};