r8a77970.dtsi (c6380ecd8e9bee7aba3d9a5a94b58168244c4a61) r8a77970.dtsi (95c969d12ea19062077448a0081dc657232edd1d)
1/*
2 * Device Tree Source for the r8a77970 SoC
3 *
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any

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87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
88 IRQ_TYPE_LEVEL_HIGH)>;
89 clocks = <&cpg CPG_MOD 408>;
90 clock-names = "clk";
91 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
92 resets = <&cpg 408>;
93 };
94
1/*
2 * Device Tree Source for the r8a77970 SoC
3 *
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any

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87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
88 IRQ_TYPE_LEVEL_HIGH)>;
89 clocks = <&cpg CPG_MOD 408>;
90 clock-names = "clk";
91 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
92 resets = <&cpg 408>;
93 };
94
95 timer {
96 compatible = "arm,armv8-timer";
97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
98 IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
100 IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
102 IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
104 IRQ_TYPE_LEVEL_LOW)>;
105 };
106
107 rwdt: watchdog@e6020000 {
108 compatible = "renesas,r8a77970-wdt",
109 "renesas,rcar-gen3-wdt";
110 reg = <0 0xe6020000 0 0x0c>;
111 clocks = <&cpg CPG_MOD 402>;
112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
113 resets = <&cpg 402>;
114 status = "disabled";

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173 compatible = "renesas,ipmmu-r8a77970";
174 reg = <0 0xe67b0000 0 0x1000>;
175 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
177 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
178 #iommu-cells = <1>;
179 };
180
95 rwdt: watchdog@e6020000 {
96 compatible = "renesas,r8a77970-wdt",
97 "renesas,rcar-gen3-wdt";
98 reg = <0 0xe6020000 0 0x0c>;
99 clocks = <&cpg CPG_MOD 402>;
100 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
101 resets = <&cpg 402>;
102 status = "disabled";

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161 compatible = "renesas,ipmmu-r8a77970";
162 reg = <0 0xe67b0000 0 0x1000>;
163 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
165 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
166 #iommu-cells = <1>;
167 };
168
169 pfc: pin-controller@e6060000 {
170 compatible = "renesas,pfc-r8a77970";
171 reg = <0 0xe6060000 0 0x504>;
172 };
173
174 gpio0: gpio@e6050000 {
175 compatible = "renesas,gpio-r8a77970",
176 "renesas,rcar-gen3-gpio";
177 reg = <0 0xe6050000 0 0x50>;
178 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 0 22>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&cpg CPG_MOD 912>;
185 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
186 resets = <&cpg 912>;
187 };
188
189 gpio1: gpio@e6051000 {
190 compatible = "renesas,gpio-r8a77970",
191 "renesas,rcar-gen3-gpio";
192 reg = <0 0xe6051000 0 0x50>;
193 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
194 #gpio-cells = <2>;
195 gpio-controller;
196 gpio-ranges = <&pfc 0 32 28>;
197 #interrupt-cells = <2>;
198 interrupt-controller;
199 clocks = <&cpg CPG_MOD 911>;
200 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
201 resets = <&cpg 911>;
202 };
203
204 gpio2: gpio@e6052000 {
205 compatible = "renesas,gpio-r8a77970",
206 "renesas,rcar-gen3-gpio";
207 reg = <0 0xe6052000 0 0x50>;
208 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 64 17>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&cpg CPG_MOD 910>;
215 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
216 resets = <&cpg 910>;
217 };
218
219 gpio3: gpio@e6053000 {
220 compatible = "renesas,gpio-r8a77970",
221 "renesas,rcar-gen3-gpio";
222 reg = <0 0xe6053000 0 0x50>;
223 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
224 #gpio-cells = <2>;
225 gpio-controller;
226 gpio-ranges = <&pfc 0 96 17>;
227 #interrupt-cells = <2>;
228 interrupt-controller;
229 clocks = <&cpg CPG_MOD 909>;
230 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
231 resets = <&cpg 909>;
232 };
233
234 gpio4: gpio@e6054000 {
235 compatible = "renesas,gpio-r8a77970",
236 "renesas,rcar-gen3-gpio";
237 reg = <0 0xe6054000 0 0x50>;
238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
239 #gpio-cells = <2>;
240 gpio-controller;
241 gpio-ranges = <&pfc 0 128 6>;
242 #interrupt-cells = <2>;
243 interrupt-controller;
244 clocks = <&cpg CPG_MOD 908>;
245 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
246 resets = <&cpg 908>;
247 };
248
249 gpio5: gpio@e6055000 {
250 compatible = "renesas,gpio-r8a77970",
251 "renesas,rcar-gen3-gpio";
252 reg = <0 0xe6055000 0 0x50>;
253 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
254 #gpio-cells = <2>;
255 gpio-controller;
256 gpio-ranges = <&pfc 0 160 15>;
257 #interrupt-cells = <2>;
258 interrupt-controller;
259 clocks = <&cpg CPG_MOD 907>;
260 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
261 resets = <&cpg 907>;
262 };
263
181 intc_ex: interrupt-controller@e61c0000 {
182 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 reg = <0 0xe61c0000 0 0x200>;
186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH

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395 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
396 resets = <&cpg 203>;
397 status = "disabled";
398 };
399
400 avb: ethernet@e6800000 {
401 compatible = "renesas,etheravb-r8a77970",
402 "renesas,etheravb-rcar-gen3";
264 intc_ex: interrupt-controller@e61c0000 {
265 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
266 #interrupt-cells = <2>;
267 interrupt-controller;
268 reg = <0 0xe61c0000 0 0x200>;
269 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH

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478 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
479 resets = <&cpg 203>;
480 status = "disabled";
481 };
482
483 avb: ethernet@e6800000 {
484 compatible = "renesas,etheravb-r8a77970",
485 "renesas,etheravb-rcar-gen3";
403 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
486 reg = <0 0xe6800000 0 0x800>;
404 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

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431 "ch8", "ch9", "ch10", "ch11",
432 "ch12", "ch13", "ch14", "ch15",
433 "ch16", "ch17", "ch18", "ch19",
434 "ch20", "ch21", "ch22", "ch23",
435 "ch24";
436 clocks = <&cpg CPG_MOD 812>;
437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
438 resets = <&cpg 812>;
487 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

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514 "ch8", "ch9", "ch10", "ch11",
515 "ch12", "ch13", "ch14", "ch15",
516 "ch16", "ch17", "ch18", "ch19",
517 "ch20", "ch21", "ch22", "ch23",
518 "ch24";
519 clocks = <&cpg CPG_MOD 812>;
520 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
521 resets = <&cpg 812>;
439 phy-mode = "rgmii-id";
522 phy-mode = "rgmii";
440 iommus = <&ipmmu_rt 3>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 };
444 };
523 iommus = <&ipmmu_rt 3>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 };
527 };
528
529 timer {
530 compatible = "arm,armv8-timer";
531 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
532 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
533 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
534 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
535 };
445};
536};