r8a77970.dtsi (b4f92030d5d39df427e72ace7f7db04dc8b35ddb) r8a77970.dtsi (f66598b95dbac72365f5b81ffa61ca6357af6b22)
1/*
2 * Device Tree Source for the r8a77970 SoC
3 *
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any

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630 compatible = "renesas,vsp2";
631 reg = <0 0xfea20000 0 0x8000>;
632 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cpg CPG_MOD 623>;
634 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
635 resets = <&cpg 623>;
636 renesas,fcp = <&fcpvd0>;
637 };
1/*
2 * Device Tree Source for the r8a77970 SoC
3 *
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any

--- 621 unchanged lines hidden (view full) ---

630 compatible = "renesas,vsp2";
631 reg = <0 0xfea20000 0 0x8000>;
632 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cpg CPG_MOD 623>;
634 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
635 resets = <&cpg 623>;
636 renesas,fcp = <&fcpvd0>;
637 };
638
639 du: display@feb00000 {
640 compatible = "renesas,du-r8a77970";
641 reg = <0 0xfeb00000 0 0x80000>;
642 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cpg CPG_MOD 724>;
644 clock-names = "du.0";
645 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
646 resets = <&cpg 724>;
647 vsps = <&vspd0>;
648 status = "disabled";
649
650 ports {
651 #address-cells = <1>;
652 #size-cells = <0>;
653
654 port@0 {
655 reg = <0>;
656 du_out_rgb: endpoint {
657 };
658 };
659
660 port@1 {
661 reg = <1>;
662 du_out_lvds0: endpoint {
663 };
664 };
665 };
666 };
638 };
639
640 timer {
641 compatible = "arm,armv8-timer";
642 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
643 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
644 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
645 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
646 };
647};
667 };
668
669 timer {
670 compatible = "arm,armv8-timer";
671 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
672 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
673 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
674 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
675 };
676};