r8a77965.dtsi (747bbcd3aacd95fe200cdda415dba02e872946b5) r8a77965.dtsi (6af663af3c46300032fd7a783bdc3e585035438f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

--- 1089 unchanged lines hidden (view full) ---

1098 };
1099
1100 canfd: can@e66c0000 {
1101 compatible = "renesas,r8a77965-canfd",
1102 "renesas,rcar-gen3-canfd";
1103 reg = <0 0xe66c0000 0 0x8000>;
1104 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

--- 1089 unchanged lines hidden (view full) ---

1098 };
1099
1100 canfd: can@e66c0000 {
1101 compatible = "renesas,r8a77965-canfd",
1102 "renesas,rcar-gen3-canfd";
1103 reg = <0 0xe66c0000 0 0x8000>;
1104 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1106 interrupt-names = "ch_int", "g_int";
1106 clocks = <&cpg CPG_MOD 914>,
1107 <&cpg CPG_CORE R8A77965_CLK_CANFD>,
1108 <&can_clk>;
1109 clock-names = "fck", "canfd", "can_clk";
1110 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
1111 assigned-clock-rates = <40000000>;
1112 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1113 resets = <&cpg 914>;

--- 1784 unchanged lines hidden --- 		1107 clocks = <&cpg CPG_MOD 914>,
1108 <&cpg CPG_CORE R8A77965_CLK_CANFD>,
1109 <&can_clk>;
1110 clock-names = "fck", "canfd", "can_clk";
1111 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
1112 assigned-clock-rates = <40000000>;
1113 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1114 resets = <&cpg 914>;

--- 1784 unchanged lines hidden ---