r8a77965.dtsi (281a94b0f2f0775a2b7825c18bccf7e4c922b7b3) r8a77965.dtsi (4e4c17c6c3907dfc34051cc450a78a38fb371b4f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

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450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&cpg CPG_MOD 407>;
454 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
455 resets = <&cpg 407>;
456 };
457
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

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450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&cpg CPG_MOD 407>;
454 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
455 resets = <&cpg 407>;
456 };
457
458 tmu0: timer@e61e0000 {
459 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
460 reg = <0 0xe61e0000 0 0x30>;
461 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cpg CPG_MOD 125>;
465 clock-names = "fck";
466 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
467 resets = <&cpg 125>;
468 status = "disabled";
469 };
470
471 tmu1: timer@e6fc0000 {
472 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
473 reg = <0 0xe6fc0000 0 0x30>;
474 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 124>;
478 clock-names = "fck";
479 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
480 resets = <&cpg 124>;
481 status = "disabled";
482 };
483
484 tmu2: timer@e6fd0000 {
485 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
486 reg = <0 0xe6fd0000 0 0x30>;
487 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cpg CPG_MOD 123>;
491 clock-names = "fck";
492 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
493 resets = <&cpg 123>;
494 status = "disabled";
495 };
496
497 tmu3: timer@e6fe0000 {
498 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
499 reg = <0 0xe6fe0000 0 0x30>;
500 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cpg CPG_MOD 122>;
504 clock-names = "fck";
505 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
506 resets = <&cpg 122>;
507 status = "disabled";
508 };
509
510 tmu4: timer@ffc00000 {
511 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
512 reg = <0 0xffc00000 0 0x30>;
513 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cpg CPG_MOD 121>;
517 clock-names = "fck";
518 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
519 resets = <&cpg 121>;
520 status = "disabled";
521 };
522
458 i2c0: i2c@e6500000 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "renesas,i2c-r8a77965",
462 "renesas,rcar-gen3-i2c";
463 reg = <0 0xe6500000 0 0x40>;
464 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cpg CPG_MOD 931>;

--- 2327 unchanged lines hidden --- 		523 i2c0: i2c@e6500000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "renesas,i2c-r8a77965",
527 "renesas,rcar-gen3-i2c";
528 reg = <0 0xe6500000 0 0x40>;
529 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cpg CPG_MOD 931>;

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