r8a77965.dtsi (0b65a9ad25b3f68ab2f6a1a202fe1df28b08e28a) r8a77965.dtsi (55697cbb44e4f7ea8369f19fa95115dbf066708c)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77965 SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

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699 clocks = <&cpg CPG_MOD 217>;
700 clock-names = "fck";
701 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
702 resets = <&cpg 217>;
703 #dma-cells = <1>;
704 dma-channels = <16>;
705 };
706
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77965 SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.

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699 clocks = <&cpg CPG_MOD 217>;
700 clock-names = "fck";
701 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
702 resets = <&cpg 217>;
703 #dma-cells = <1>;
704 dma-channels = <16>;
705 };
706
707 ipmmu_ds0: mmu@e6740000 {
708 compatible = "renesas,ipmmu-r8a77965";
709 reg = <0 0xe6740000 0 0x1000>;
710 renesas,ipmmu-main = <&ipmmu_mm 0>;
711 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
712 #iommu-cells = <1>;
713 };
714
715 ipmmu_ds1: mmu@e7740000 {
716 compatible = "renesas,ipmmu-r8a77965";
717 reg = <0 0xe7740000 0 0x1000>;
718 renesas,ipmmu-main = <&ipmmu_mm 1>;
719 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
720 #iommu-cells = <1>;
721 };
722
723 ipmmu_hc: mmu@e6570000 {
724 compatible = "renesas,ipmmu-r8a77965";
725 reg = <0 0xe6570000 0 0x1000>;
726 renesas,ipmmu-main = <&ipmmu_mm 2>;
727 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
728 #iommu-cells = <1>;
729 };
730
731 ipmmu_ir: mmu@ff8b0000 {
732 compatible = "renesas,ipmmu-r8a77965";
733 reg = <0 0xff8b0000 0 0x1000>;
734 renesas,ipmmu-main = <&ipmmu_mm 3>;
735 power-domains = <&sysc R8A77965_PD_A3IR>;
736 #iommu-cells = <1>;
737 };
738
739 ipmmu_mm: mmu@e67b0000 {
740 compatible = "renesas,ipmmu-r8a77965";
741 reg = <0 0xe67b0000 0 0x1000>;
742 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
744 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
745 #iommu-cells = <1>;
746 };
747
748 ipmmu_mp: mmu@ec670000 {
749 compatible = "renesas,ipmmu-r8a77965";
750 reg = <0 0xec670000 0 0x1000>;
751 renesas,ipmmu-main = <&ipmmu_mm 4>;
752 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
753 #iommu-cells = <1>;
754 };
755
756 ipmmu_pv0: mmu@fd800000 {
757 compatible = "renesas,ipmmu-r8a77965";
758 reg = <0 0xfd800000 0 0x1000>;
759 renesas,ipmmu-main = <&ipmmu_mm 6>;
760 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
761 #iommu-cells = <1>;
762 };
763
764 ipmmu_rt: mmu@ffc80000 {
765 compatible = "renesas,ipmmu-r8a77965";
766 reg = <0 0xffc80000 0 0x1000>;
767 renesas,ipmmu-main = <&ipmmu_mm 10>;
768 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
769 #iommu-cells = <1>;
770 };
771
772 ipmmu_vc0: mmu@fe6b0000 {
773 compatible = "renesas,ipmmu-r8a77965";
774 reg = <0 0xfe6b0000 0 0x1000>;
775 renesas,ipmmu-main = <&ipmmu_mm 12>;
776 power-domains = <&sysc R8A77965_PD_A3VC>;
777 #iommu-cells = <1>;
778 };
779
780 ipmmu_vi0: mmu@febd0000 {
781 compatible = "renesas,ipmmu-r8a77965";
782 reg = <0 0xfebd0000 0 0x1000>;
783 renesas,ipmmu-main = <&ipmmu_mm 14>;
784 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
785 #iommu-cells = <1>;
786 };
787
788 ipmmu_vp0: mmu@fe990000 {
789 compatible = "renesas,ipmmu-r8a77965";
790 reg = <0 0xfe990000 0 0x1000>;
791 renesas,ipmmu-main = <&ipmmu_mm 16>;
792 power-domains = <&sysc R8A77965_PD_A3VP>;
793 #iommu-cells = <1>;
794 };
795
707 avb: ethernet@e6800000 {
708 compatible = "renesas,etheravb-r8a77965",
709 "renesas,etheravb-rcar-gen3";
710 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
711 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

--- 1107 unchanged lines hidden --- 		796 avb: ethernet@e6800000 {
797 compatible = "renesas,etheravb-r8a77965",
798 "renesas,etheravb-rcar-gen3";
799 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
800 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

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