r8a77961.dtsi (a1ff5a7d78a036d6c2178ee5acd6ba4946243800) r8a77961.dtsi (fc50fd9ab56d810a49ee070ec41c19dd47de5d1c)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2497 };
2498
2499 fcpf0: fcp@fe950000 {
2500 compatible = "renesas,fcpf";
2501 reg = <0 0xfe950000 0 0x200>;
2502 clocks = <&cpg CPG_MOD 615>;
2503 power-domains = <&sysc R8A77961_PD_A3VC>;
2504 resets = <&cpg 615>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2497 };
2498
2499 fcpf0: fcp@fe950000 {
2500 compatible = "renesas,fcpf";
2501 reg = <0 0xfe950000 0 0x200>;
2502 clocks = <&cpg CPG_MOD 615>;
2503 power-domains = <&sysc R8A77961_PD_A3VC>;
2504 resets = <&cpg 615>;
2505 iommus = <&ipmmu_vc0 16>;
2505 };
2506
2507 fcpvb0: fcp@fe96f000 {
2508 compatible = "renesas,fcpv";
2509 reg = <0 0xfe96f000 0 0x200>;
2510 clocks = <&cpg CPG_MOD 607>;
2511 power-domains = <&sysc R8A77961_PD_A3VC>;
2512 resets = <&cpg 607>;
2506 };
2507
2508 fcpvb0: fcp@fe96f000 {
2509 compatible = "renesas,fcpv";
2510 reg = <0 0xfe96f000 0 0x200>;
2511 clocks = <&cpg CPG_MOD 607>;
2512 power-domains = <&sysc R8A77961_PD_A3VC>;
2513 resets = <&cpg 607>;
2514 iommus = <&ipmmu_vi0 5>;
2513 };
2514
2515 fcpvi0: fcp@fe9af000 {
2516 compatible = "renesas,fcpv";
2517 reg = <0 0xfe9af000 0 0x200>;
2518 clocks = <&cpg CPG_MOD 611>;
2519 power-domains = <&sysc R8A77961_PD_A3VC>;
2520 resets = <&cpg 611>;

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2516
2517 fcpvi0: fcp@fe9af000 {
2518 compatible = "renesas,fcpv";
2519 reg = <0 0xfe9af000 0 0x200>;
2520 clocks = <&cpg CPG_MOD 611>;
2521 power-domains = <&sysc R8A77961_PD_A3VC>;
2522 resets = <&cpg 611>;

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