r8a77961.dtsi (9c3a985f88fa4de82bf4bda906095ce6444e9039) r8a77961.dtsi (86d904b6ef9f5e67a28e0a0bb58df898c08ae0b8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2440 #address-cells = <3>;
2441 #size-cells = <2>;
2442 bus-range = <0x00 0xff>;
2443 device_type = "pci";
2444 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2445 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2446 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2447 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2440 #address-cells = <3>;
2441 #size-cells = <2>;
2442 bus-range = <0x00 0xff>;
2443 device_type = "pci";
2444 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2445 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2446 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2447 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2448 /* Map all possible DDR as inbound ranges */
2449 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2448 /* Map all possible DDR/IOMMU as inbound ranges */
2449 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2450 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2452 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2453 #interrupt-cells = <1>;
2454 interrupt-map-mask = <0 0 0 0>;
2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2456 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2457 clock-names = "pcie", "pcie_bus";
2458 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2459 resets = <&cpg 319>;
2450 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2452 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2453 #interrupt-cells = <1>;
2454 interrupt-map-mask = <0 0 0 0>;
2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2456 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2457 clock-names = "pcie", "pcie_bus";
2458 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2459 resets = <&cpg 319>;
2460 iommu-map = <0 &ipmmu_hc 0 1>;
2461 iommu-map-mask = <0>;
2460 status = "disabled";
2461 };
2462
2463 pciec1: pcie@ee800000 {
2464 compatible = "renesas,pcie-r8a77961",
2465 "renesas,pcie-rcar-gen3";
2466 reg = <0 0xee800000 0 0x80000>;
2467 #address-cells = <3>;
2468 #size-cells = <2>;
2469 bus-range = <0x00 0xff>;
2470 device_type = "pci";
2471 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2472 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2473 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2474 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2462 status = "disabled";
2463 };
2464
2465 pciec1: pcie@ee800000 {
2466 compatible = "renesas,pcie-r8a77961",
2467 "renesas,pcie-rcar-gen3";
2468 reg = <0 0xee800000 0 0x80000>;
2469 #address-cells = <3>;
2470 #size-cells = <2>;
2471 bus-range = <0x00 0xff>;
2472 device_type = "pci";
2473 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2474 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2475 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2476 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2475 /* Map all possible DDR as inbound ranges */
2476 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2477 /* Map all possible DDR/IOMMU as inbound ranges */
2478 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2477 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2478 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2479 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2480 #interrupt-cells = <1>;
2481 interrupt-map-mask = <0 0 0 0>;
2482 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2483 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2484 clock-names = "pcie", "pcie_bus";
2485 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2486 resets = <&cpg 318>;
2479 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2480 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2481 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2482 #interrupt-cells = <1>;
2483 interrupt-map-mask = <0 0 0 0>;
2484 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2485 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2486 clock-names = "pcie", "pcie_bus";
2487 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2488 resets = <&cpg 318>;
2489 iommu-map = <0 &ipmmu_hc 1 1>;
2490 iommu-map-mask = <0>;
2487 status = "disabled";
2488 };
2489
2490 fcpf0: fcp@fe950000 {
2491 compatible = "renesas,fcpf";
2492 reg = <0 0xfe950000 0 0x200>;
2493 clocks = <&cpg CPG_MOD 615>;
2494 power-domains = <&sysc R8A77961_PD_A3VC>;

--- 403 unchanged lines hidden --- 		2491 status = "disabled";
2492 };
2493
2494 fcpf0: fcp@fe950000 {
2495 compatible = "renesas,fcpf";
2496 reg = <0 0xfe950000 0 0x200>;
2497 clocks = <&cpg CPG_MOD 615>;
2498 power-domains = <&sysc R8A77961_PD_A3VC>;

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