r8a77961.dtsi (9ab847043f24f6e83eb905230d050a754e790759) r8a77961.dtsi (298b0c8b2a5fb98bab2dc7846adf0f5e3e3f3d8a)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

--- 1970 unchanged lines hidden (view full) ---

1979 compatible = "renesas,fcpv";
1980 reg = <0 0xfea37000 0 0x200>;
1981 clocks = <&cpg CPG_MOD 601>;
1982 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1983 resets = <&cpg 601>;
1984 iommus = <&ipmmu_vi0 10>;
1985 };
1986
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

--- 1970 unchanged lines hidden (view full) ---

1979 compatible = "renesas,fcpv";
1980 reg = <0 0xfea37000 0 0x200>;
1981 clocks = <&cpg CPG_MOD 601>;
1982 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1983 resets = <&cpg 601>;
1984 iommus = <&ipmmu_vi0 10>;
1985 };
1986
1987 vspb: vsp@fe960000 {
1988 compatible = "renesas,vsp2";
1989 reg = <0 0xfe960000 0 0x8000>;
1990 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1991 clocks = <&cpg CPG_MOD 626>;
1992 power-domains = <&sysc R8A77961_PD_A3VC>;
1993 resets = <&cpg 626>;
1994
1995 renesas,fcp = <&fcpvb0>;
1996 };
1997
1998 vspd0: vsp@fea20000 {
1999 compatible = "renesas,vsp2";
2000 reg = <0 0xfea20000 0 0x5000>;
2001 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2002 clocks = <&cpg CPG_MOD 623>;
2003 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2004 resets = <&cpg 623>;
2005
2006 renesas,fcp = <&fcpvd0>;
2007 };
2008
2009 vspd1: vsp@fea28000 {
2010 compatible = "renesas,vsp2";
2011 reg = <0 0xfea28000 0 0x5000>;
2012 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2013 clocks = <&cpg CPG_MOD 622>;
2014 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2015 resets = <&cpg 622>;
2016
2017 renesas,fcp = <&fcpvd1>;
2018 };
2019
2020 vspd2: vsp@fea30000 {
2021 compatible = "renesas,vsp2";
2022 reg = <0 0xfea30000 0 0x5000>;
2023 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2024 clocks = <&cpg CPG_MOD 621>;
2025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2026 resets = <&cpg 621>;
2027
2028 renesas,fcp = <&fcpvd2>;
2029 };
2030
2031 vspi0: vsp@fe9a0000 {
2032 compatible = "renesas,vsp2";
2033 reg = <0 0xfe9a0000 0 0x8000>;
2034 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2035 clocks = <&cpg CPG_MOD 631>;
2036 power-domains = <&sysc R8A77961_PD_A3VC>;
2037 resets = <&cpg 631>;
2038
2039 renesas,fcp = <&fcpvi0>;
2040 };
2041
1987 csi20: csi2@fea80000 {
1988 reg = <0 0xfea80000 0 0x10000>;
1989 /* placeholder */
1990
1991 ports {
1992 #address-cells = <1>;
1993 #size-cells = <0>;
1994

--- 163 unchanged lines hidden --- 		2042 csi20: csi2@fea80000 {
2043 reg = <0 0xfea80000 0 0x10000>;
2044 /* placeholder */
2045
2046 ports {
2047 #address-cells = <1>;
2048 #size-cells = <0>;
2049

--- 163 unchanged lines hidden ---