r8a77961.dtsi (2bc0aa18ee9f34613876f6ac7bf944ad65d63e17) r8a77961.dtsi (f191fba76916dc18c41cf6183d71dbf9a1d821c8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2396 clock-names = "core", "clkh";
2397 max-frequency = <200000000>;
2398 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2399 resets = <&cpg 311>;
2400 iommus = <&ipmmu_ds1 35>;
2401 status = "disabled";
2402 };
2403
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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2396 clock-names = "core", "clkh";
2397 max-frequency = <200000000>;
2398 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2399 resets = <&cpg 311>;
2400 iommus = <&ipmmu_ds1 35>;
2401 status = "disabled";
2402 };
2403
2404 rpc: spi@ee200000 {
2405 compatible = "renesas,r8a77961-rpc-if",
2406 "renesas,rcar-gen3-rpc-if";
2407 reg = <0 0xee200000 0 0x200>,
2408 <0 0x08000000 0 0x04000000>,
2409 <0 0xee208000 0 0x100>;
2410 reg-names = "regs", "dirmap", "wbuf";
2411 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2412 clocks = <&cpg CPG_MOD 917>;
2413 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2414 resets = <&cpg 917>;
2415 #address-cells = <1>;
2416 #size-cells = <0>;
2417 status = "disabled";
2418 };
2419
2404 gic: interrupt-controller@f1010000 {
2405 compatible = "arm,gic-400";
2406 #interrupt-cells = <3>;
2407 #address-cells = <0>;
2408 interrupt-controller;
2409 reg = <0x0 0xf1010000 0 0x1000>,
2410 <0x0 0xf1020000 0 0x20000>,
2411 <0x0 0xf1040000 0 0x20000>,

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2420 gic: interrupt-controller@f1010000 {
2421 compatible = "arm,gic-400";
2422 #interrupt-cells = <3>;
2423 #address-cells = <0>;
2424 interrupt-controller;
2425 reg = <0x0 0xf1010000 0 0x1000>,
2426 <0x0 0xf1020000 0 0x20000>,
2427 <0x0 0xf1040000 0 0x20000>,

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