r8a77961.dtsi (0f69403d2535ffc7200a8414cf3ca66a49b0d741) r8a77961.dtsi (8bd35145975d9f9f92bfd508a6f705f9bf6c50a2)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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878 clocks = <&cpg CPG_MOD 217>;
879 clock-names = "fck";
880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
881 resets = <&cpg 217>;
882 #dma-cells = <1>;
883 dma-channels = <16>;
884 };
885
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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878 clocks = <&cpg CPG_MOD 217>;
879 clock-names = "fck";
880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
881 resets = <&cpg 217>;
882 #dma-cells = <1>;
883 dma-channels = <16>;
884 };
885
886 ipmmu_ds0: iommu@e6740000 {
887 compatible = "renesas,ipmmu-r8a77961";
888 reg = <0 0xe6740000 0 0x1000>;
889 renesas,ipmmu-main = <&ipmmu_mm 0>;
890 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
891 #iommu-cells = <1>;
892 };
893
894 ipmmu_ds1: iommu@e7740000 {
895 compatible = "renesas,ipmmu-r8a77961";
896 reg = <0 0xe7740000 0 0x1000>;
897 renesas,ipmmu-main = <&ipmmu_mm 1>;
898 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
899 #iommu-cells = <1>;
900 };
901
902 ipmmu_hc: iommu@e6570000 {
903 compatible = "renesas,ipmmu-r8a77961";
904 reg = <0 0xe6570000 0 0x1000>;
905 renesas,ipmmu-main = <&ipmmu_mm 2>;
906 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
907 #iommu-cells = <1>;
908 };
909
910 ipmmu_ir: iommu@ff8b0000 {
911 compatible = "renesas,ipmmu-r8a77961";
912 reg = <0 0xff8b0000 0 0x1000>;
913 renesas,ipmmu-main = <&ipmmu_mm 3>;
914 power-domains = <&sysc R8A77961_PD_A3IR>;
915 #iommu-cells = <1>;
916 };
917
918 ipmmu_mm: iommu@e67b0000 {
919 compatible = "renesas,ipmmu-r8a77961";
920 reg = <0 0xe67b0000 0 0x1000>;
921 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
923 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
924 #iommu-cells = <1>;
925 };
926
927 ipmmu_mp: iommu@ec670000 {
928 compatible = "renesas,ipmmu-r8a77961";
929 reg = <0 0xec670000 0 0x1000>;
930 renesas,ipmmu-main = <&ipmmu_mm 4>;
931 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
932 #iommu-cells = <1>;
933 };
934
935 ipmmu_pv0: iommu@fd800000 {
936 compatible = "renesas,ipmmu-r8a77961";
937 reg = <0 0xfd800000 0 0x1000>;
938 renesas,ipmmu-main = <&ipmmu_mm 5>;
939 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
940 #iommu-cells = <1>;
941 };
942
943 ipmmu_pv1: iommu@fd950000 {
944 compatible = "renesas,ipmmu-r8a77961";
945 reg = <0 0xfd950000 0 0x1000>;
946 renesas,ipmmu-main = <&ipmmu_mm 6>;
947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
948 #iommu-cells = <1>;
949 };
950
951 ipmmu_rt: iommu@ffc80000 {
952 compatible = "renesas,ipmmu-r8a77961";
953 reg = <0 0xffc80000 0 0x1000>;
954 renesas,ipmmu-main = <&ipmmu_mm 7>;
955 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
956 #iommu-cells = <1>;
957 };
958
959 ipmmu_vc0: iommu@fe6b0000 {
960 compatible = "renesas,ipmmu-r8a77961";
961 reg = <0 0xfe6b0000 0 0x1000>;
962 renesas,ipmmu-main = <&ipmmu_mm 8>;
963 power-domains = <&sysc R8A77961_PD_A3VC>;
964 #iommu-cells = <1>;
965 };
966
967 ipmmu_vi0: iommu@febd0000 {
968 compatible = "renesas,ipmmu-r8a77961";
969 reg = <0 0xfebd0000 0 0x1000>;
970 renesas,ipmmu-main = <&ipmmu_mm 9>;
971 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
972 #iommu-cells = <1>;
973 };
974
886 avb: ethernet@e6800000 {
887 compatible = "renesas,etheravb-r8a77961",
888 "renesas,etheravb-rcar-gen3";
889 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
890 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

--- 656 unchanged lines hidden --- 		975 avb: ethernet@e6800000 {
976 compatible = "renesas,etheravb-r8a77961",
977 "renesas,etheravb-rcar-gen3";
978 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
979 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

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