r8a77960.dtsi (a582013b7b1a6fbe9e896b5686887bc804800fe0) r8a77960.dtsi (d745c72da921acdf38d68681d5fc2ff113b78f55)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7796-cpg-mssr.h>

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2822 };
2823
2824 du: display@feb00000 {
2825 compatible = "renesas,du-r8a7796";
2826 reg = <0 0xfeb00000 0 0x70000>;
2827 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2828 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2829 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7796-cpg-mssr.h>

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2822 };
2823
2824 du: display@feb00000 {
2825 compatible = "renesas,du-r8a7796";
2826 reg = <0 0xfeb00000 0 0x70000>;
2827 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2828 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2829 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2830 clocks = <&cpg CPG_MOD 724>,
2831 <&cpg CPG_MOD 723>,
2830 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2832 <&cpg CPG_MOD 722>;
2833 clock-names = "du.0", "du.1", "du.2";
2831 <&cpg CPG_MOD 722>;
2832 clock-names = "du.0", "du.1", "du.2";
2833 resets = <&cpg 724>, <&cpg 722>;
2834 reset-names = "du.0", "du.2";
2834
2835 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2836 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2837
2838 status = "disabled";
2839
2840 ports {
2841 #address-cells = <1>;

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2836 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2837 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2838
2839 status = "disabled";
2840
2841 ports {
2842 #address-cells = <1>;

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