r8a77960.dtsi (281a94b0f2f0775a2b7825c18bccf7e4c922b7b3) r8a77960.dtsi (4e4c17c6c3907dfc34051cc450a78a38fb371b4f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7796-cpg-mssr.h>

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580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 407>;
584 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 407>;
586 };
587
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7796-cpg-mssr.h>

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580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 407>;
584 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 407>;
586 };
587
588 tmu0: timer@e61e0000 {
589 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
590 reg = <0 0xe61e0000 0 0x30>;
591 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cpg CPG_MOD 125>;
595 clock-names = "fck";
596 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
597 resets = <&cpg 125>;
598 status = "disabled";
599 };
600
601 tmu1: timer@e6fc0000 {
602 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
603 reg = <0 0xe6fc0000 0 0x30>;
604 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cpg CPG_MOD 124>;
608 clock-names = "fck";
609 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
610 resets = <&cpg 124>;
611 status = "disabled";
612 };
613
614 tmu2: timer@e6fd0000 {
615 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
616 reg = <0 0xe6fd0000 0 0x30>;
617 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cpg CPG_MOD 123>;
621 clock-names = "fck";
622 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
623 resets = <&cpg 123>;
624 status = "disabled";
625 };
626
627 tmu3: timer@e6fe0000 {
628 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
629 reg = <0 0xe6fe0000 0 0x30>;
630 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cpg CPG_MOD 122>;
634 clock-names = "fck";
635 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
636 resets = <&cpg 122>;
637 status = "disabled";
638 };
639
640 tmu4: timer@ffc00000 {
641 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
642 reg = <0 0xffc00000 0 0x30>;
643 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cpg CPG_MOD 121>;
647 clock-names = "fck";
648 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
649 resets = <&cpg 121>;
650 status = "disabled";
651 };
652
588 i2c0: i2c@e6500000 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "renesas,i2c-r8a7796",
592 "renesas,rcar-gen3-i2c";
593 reg = <0 0xe6500000 0 0x40>;
594 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cpg CPG_MOD 931>;

--- 2389 unchanged lines hidden --- 		653 i2c0: i2c@e6500000 {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "renesas,i2c-r8a7796",
657 "renesas,rcar-gen3-i2c";
658 reg = <0 0xe6500000 0 0x40>;
659 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&cpg CPG_MOD 931>;

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