r8a77951.dtsi (eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1) r8a77951.dtsi (7744b393c95ac470a3ac279fa277e50d947f1bea)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

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57
58 /* External CAN clock - to be overridden by boards that provide it */
59 can_clk: can {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <0>;
63 };
64
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

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57
58 /* External CAN clock - to be overridden by boards that provide it */
59 can_clk: can {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <0>;
63 };
64
65 cluster0_opp: opp_table0 {
65 cluster0_opp: opp-table-0 {
66 compatible = "operating-points-v2";
67 opp-shared;
68
69 opp-500000000 {
70 opp-hz = /bits/ 64 <500000000>;
71 opp-microvolt = <830000>;
72 clock-latency-ns = <300000>;
73 };

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91 opp-1700000000 {
92 opp-hz = /bits/ 64 <1700000000>;
93 opp-microvolt = <960000>;
94 clock-latency-ns = <300000>;
95 turbo-mode;
96 };
97 };
98
66 compatible = "operating-points-v2";
67 opp-shared;
68
69 opp-500000000 {
70 opp-hz = /bits/ 64 <500000000>;
71 opp-microvolt = <830000>;
72 clock-latency-ns = <300000>;
73 };

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91 opp-1700000000 {
92 opp-hz = /bits/ 64 <1700000000>;
93 opp-microvolt = <960000>;
94 clock-latency-ns = <300000>;
95 turbo-mode;
96 };
97 };
98
99 cluster1_opp: opp_table1 {
99 cluster1_opp: opp-table-1 {
100 compatible = "operating-points-v2";
101 opp-shared;
102
103 opp-800000000 {
104 opp-hz = /bits/ 64 <800000000>;
105 opp-microvolt = <820000>;
106 clock-latency-ns = <300000>;
107 };

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100 compatible = "operating-points-v2";
101 opp-shared;
102
103 opp-800000000 {
104 opp-hz = /bits/ 64 <800000000>;
105 opp-microvolt = <820000>;
106 clock-latency-ns = <300000>;
107 };

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