r8a77951.dtsi (9ddb236f13594b34a12dacf69a5adca7a1aef35e) r8a77951.dtsi (a2053990f3275e715d69c208d8c0040cac0df593)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

--- 476 unchanged lines hidden (view full) ---

485 gpio-ranges = <&pfc 0 224 4>;
486 #interrupt-cells = <2>;
487 interrupt-controller;
488 clocks = <&cpg CPG_MOD 905>;
489 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
490 resets = <&cpg 905>;
491 };
492
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

--- 476 unchanged lines hidden (view full) ---

485 gpio-ranges = <&pfc 0 224 4>;
486 #interrupt-cells = <2>;
487 interrupt-controller;
488 clocks = <&cpg CPG_MOD 905>;
489 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
490 resets = <&cpg 905>;
491 };
492
493 pfc: pin-controller@e6060000 {
493 pfc: pinctrl@e6060000 {
494 compatible = "renesas,pfc-r8a7795";
495 reg = <0 0xe6060000 0 0x50c>;
496 };
497
498 cmt0: timer@e60f0000 {
499 compatible = "renesas,r8a7795-cmt0",
500 "renesas,rcar-gen3-cmt0";
501 reg = <0 0xe60f0000 0 0x1004>;

--- 2839 unchanged lines hidden --- 		494 compatible = "renesas,pfc-r8a7795";
495 reg = <0 0xe6060000 0 0x50c>;
496 };
497
498 cmt0: timer@e60f0000 {
499 compatible = "renesas,r8a7795-cmt0",
500 "renesas,rcar-gen3-cmt0";
501 reg = <0 0xe60f0000 0 0x1004>;

--- 2839 unchanged lines hidden ---