r8a77951.dtsi (9c3a985f88fa4de82bf4bda906095ce6444e9039) r8a77951.dtsi (86d904b6ef9f5e67a28e0a0bb58df898c08ae0b8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

--- 2764 unchanged lines hidden (view full) ---

2773 #address-cells = <3>;
2774 #size-cells = <2>;
2775 bus-range = <0x00 0xff>;
2776 device_type = "pci";
2777 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2778 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2779 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2780 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

--- 2764 unchanged lines hidden (view full) ---

2773 #address-cells = <3>;
2774 #size-cells = <2>;
2775 bus-range = <0x00 0xff>;
2776 device_type = "pci";
2777 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2778 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2779 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2780 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2781 /* Map all possible DDR as inbound ranges */
2782 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2781 /* Map all possible DDR/IOMMU as inbound ranges */
2782 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2783 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2786 #interrupt-cells = <1>;
2787 interrupt-map-mask = <0 0 0 0>;
2788 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2790 clock-names = "pcie", "pcie_bus";
2791 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2792 resets = <&cpg 319>;
2783 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2786 #interrupt-cells = <1>;
2787 interrupt-map-mask = <0 0 0 0>;
2788 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2790 clock-names = "pcie", "pcie_bus";
2791 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2792 resets = <&cpg 319>;
2793 iommu-map = <0 &ipmmu_hc 0 1>;
2794 iommu-map-mask = <0>;
2793 status = "disabled";
2794 };
2795
2796 pciec1: pcie@ee800000 {
2797 compatible = "renesas,pcie-r8a7795",
2798 "renesas,pcie-rcar-gen3";
2799 reg = <0 0xee800000 0 0x80000>;
2800 #address-cells = <3>;
2801 #size-cells = <2>;
2802 bus-range = <0x00 0xff>;
2803 device_type = "pci";
2804 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2805 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2806 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2807 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2795 status = "disabled";
2796 };
2797
2798 pciec1: pcie@ee800000 {
2799 compatible = "renesas,pcie-r8a7795",
2800 "renesas,pcie-rcar-gen3";
2801 reg = <0 0xee800000 0 0x80000>;
2802 #address-cells = <3>;
2803 #size-cells = <2>;
2804 bus-range = <0x00 0xff>;
2805 device_type = "pci";
2806 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2807 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2808 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2809 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2808 /* Map all possible DDR as inbound ranges */
2809 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2810 /* Map all possible DDR/IOMMU as inbound ranges */
2811 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2810 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2811 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2813 #interrupt-cells = <1>;
2814 interrupt-map-mask = <0 0 0 0>;
2815 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2816 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2817 clock-names = "pcie", "pcie_bus";
2818 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2819 resets = <&cpg 318>;
2812 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2813 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2815 #interrupt-cells = <1>;
2816 interrupt-map-mask = <0 0 0 0>;
2817 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2818 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2819 clock-names = "pcie", "pcie_bus";
2820 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2821 resets = <&cpg 318>;
2822 iommu-map = <0 &ipmmu_hc 1 1>;
2823 iommu-map-mask = <0>;
2820 status = "disabled";
2821 };
2822
2823 pciec0_ep: pcie-ep@fe000000 {
2824 compatible = "renesas,r8a7795-pcie-ep",
2825 "renesas,rcar-gen3-pcie-ep";
2826 reg = <0x0 0xfe000000 0 0x80000>,
2827 <0x0 0xfe100000 0 0x100000>,

--- 654 unchanged lines hidden --- 		2824 status = "disabled";
2825 };
2826
2827 pciec0_ep: pcie-ep@fe000000 {
2828 compatible = "renesas,r8a7795-pcie-ep",
2829 "renesas,rcar-gen3-pcie-ep";
2830 reg = <0x0 0xfe000000 0 0x80000>,
2831 <0x0 0xfe100000 0 0x100000>,

--- 654 unchanged lines hidden ---