r8a774e1.dtsi (96ebdb7a87917fd6ee74f46024ca756cc3d3d1ce) r8a774e1.dtsi (8e340e7560d1d4db3b7ed5c010d3460de8ff0c1e)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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29 };
30
31 audio_clk_c: audio_clk_c {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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29 };
30
31 audio_clk_c: audio_clk_c {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
37 /* External CAN clock - to be overridden by boards that provide it */
38 can_clk: can {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
42 };
43
37 cluster0_opp: opp_table0 {
38 compatible = "operating-points-v2";
39 opp-shared;
40
41 opp-500000000 {
42 opp-hz = /bits/ 64 <500000000>;
43 opp-microvolt = <820000>;
44 clock-latency-ns = <300000>;

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1134 phy-mode = "rgmii";
1135 iommus = <&ipmmu_ds0 16>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 status = "disabled";
1139 };
1140
1141 can0: can@e6c30000 {
44 cluster0_opp: opp_table0 {
45 compatible = "operating-points-v2";
46 opp-shared;
47
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <820000>;
51 clock-latency-ns = <300000>;

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1141 phy-mode = "rgmii";
1142 iommus = <&ipmmu_ds0 16>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 status = "disabled";
1146 };
1147
1148 can0: can@e6c30000 {
1149 compatible = "renesas,can-r8a774e1",
1150 "renesas,rcar-gen3-can";
1142 reg = <0 0xe6c30000 0 0x1000>;
1151 reg = <0 0xe6c30000 0 0x1000>;
1152 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1153 clocks = <&cpg CPG_MOD 916>,
1154 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1155 <&can_clk>;
1156 clock-names = "clkp1", "clkp2", "can_clk";
1157 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1158 assigned-clock-rates = <40000000>;
1159 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1160 resets = <&cpg 916>;
1143 status = "disabled";
1161 status = "disabled";
1144
1145 /* placeholder */
1146 };
1147
1148 can1: can@e6c38000 {
1162 };
1163
1164 can1: can@e6c38000 {
1165 compatible = "renesas,can-r8a774e1",
1166 "renesas,rcar-gen3-can";
1149 reg = <0 0xe6c38000 0 0x1000>;
1167 reg = <0 0xe6c38000 0 0x1000>;
1168 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&cpg CPG_MOD 915>,
1170 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1171 <&can_clk>;
1172 clock-names = "clkp1", "clkp2", "can_clk";
1173 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1174 assigned-clock-rates = <40000000>;
1175 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1176 resets = <&cpg 915>;
1150 status = "disabled";
1177 status = "disabled";
1178 };
1151
1179
1152 /* placeholder */
1180 canfd: can@e66c0000 {
1181 compatible = "renesas,r8a774e1-canfd",
1182 "renesas,rcar-gen3-canfd";
1183 reg = <0 0xe66c0000 0 0x8000>;
1184 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1186 clocks = <&cpg CPG_MOD 914>,
1187 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1188 <&can_clk>;
1189 clock-names = "fck", "canfd", "can_clk";
1190 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1191 assigned-clock-rates = <40000000>;
1192 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1193 resets = <&cpg 914>;
1194 status = "disabled";
1195
1196 channel0 {
1197 status = "disabled";
1198 };
1199
1200 channel1 {
1201 status = "disabled";
1202 };
1153 };
1154
1155 pwm0: pwm@e6e30000 {
1156 reg = <0 0xe6e30000 0 0x8>;
1157 #pwm-cells = <2>;
1158 status = "disabled";
1159
1160 /* placeholder */

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1204
1205 pwm0: pwm@e6e30000 {
1206 reg = <0 0xe6e30000 0 0x8>;
1207 #pwm-cells = <2>;
1208 status = "disabled";
1209
1210 /* placeholder */

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