r8a774e1.dtsi (747bbcd3aacd95fe200cdda415dba02e872946b5) r8a774e1.dtsi (6af663af3c46300032fd7a783bdc3e585035438f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1275 };
1276
1277 canfd: can@e66c0000 {
1278 compatible = "renesas,r8a774e1-canfd",
1279 "renesas,rcar-gen3-canfd";
1280 reg = <0 0xe66c0000 0 0x8000>;
1281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1275 };
1276
1277 canfd: can@e66c0000 {
1278 compatible = "renesas,r8a774e1-canfd",
1279 "renesas,rcar-gen3-canfd";
1280 reg = <0 0xe66c0000 0 0x8000>;
1281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1283 interrupt-names = "ch_int", "g_int";
1283 clocks = <&cpg CPG_MOD 914>,
1284 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1285 <&can_clk>;
1286 clock-names = "fck", "canfd", "can_clk";
1287 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1288 assigned-clock-rates = <40000000>;
1289 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1290 resets = <&cpg 914>;

--- 1703 unchanged lines hidden --- 		1284 clocks = <&cpg CPG_MOD 914>,
1285 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1286 <&can_clk>;
1287 clock-names = "fck", "canfd", "can_clk";
1288 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1289 assigned-clock-rates = <40000000>;
1290 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1291 resets = <&cpg 914>;

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