r8a774c0.dtsi (e700ac213a0f793fb4f83098413303e3dd080892) r8a774c0.dtsi (52e844ee9a6f460e6160736a43ef13317a91ca74)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

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1621 status = "disabled";
1622 };
1623
1624 sdhi0: mmc@ee100000 {
1625 compatible = "renesas,sdhi-r8a774c0",
1626 "renesas,rcar-gen3-sdhi";
1627 reg = <0 0xee100000 0 0x2000>;
1628 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

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1621 status = "disabled";
1622 };
1623
1624 sdhi0: mmc@ee100000 {
1625 compatible = "renesas,sdhi-r8a774c0",
1626 "renesas,rcar-gen3-sdhi";
1627 reg = <0 0xee100000 0 0x2000>;
1628 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1629 clocks = <&cpg CPG_MOD 314>;
1629 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1630 clock-names = "core", "clkh";
1630 max-frequency = <200000000>;
1631 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1632 resets = <&cpg 314>;
1633 status = "disabled";
1634 };
1635
1636 sdhi1: mmc@ee120000 {
1637 compatible = "renesas,sdhi-r8a774c0",
1638 "renesas,rcar-gen3-sdhi";
1639 reg = <0 0xee120000 0 0x2000>;
1640 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1631 max-frequency = <200000000>;
1632 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1633 resets = <&cpg 314>;
1634 status = "disabled";
1635 };
1636
1637 sdhi1: mmc@ee120000 {
1638 compatible = "renesas,sdhi-r8a774c0",
1639 "renesas,rcar-gen3-sdhi";
1640 reg = <0 0xee120000 0 0x2000>;
1641 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1641 clocks = <&cpg CPG_MOD 313>;
1642 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1643 clock-names = "core", "clkh";
1642 max-frequency = <200000000>;
1643 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1644 resets = <&cpg 313>;
1645 status = "disabled";
1646 };
1647
1648 sdhi3: mmc@ee160000 {
1649 compatible = "renesas,sdhi-r8a774c0",
1650 "renesas,rcar-gen3-sdhi";
1651 reg = <0 0xee160000 0 0x2000>;
1652 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1644 max-frequency = <200000000>;
1645 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1646 resets = <&cpg 313>;
1647 status = "disabled";
1648 };
1649
1650 sdhi3: mmc@ee160000 {
1651 compatible = "renesas,sdhi-r8a774c0",
1652 "renesas,rcar-gen3-sdhi";
1653 reg = <0 0xee160000 0 0x2000>;
1654 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1653 clocks = <&cpg CPG_MOD 311>;
1655 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1656 clock-names = "core", "clkh";
1654 max-frequency = <200000000>;
1655 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1656 resets = <&cpg 311>;
1657 status = "disabled";
1658 };
1659
1660 rpc: spi@ee200000 {
1661 compatible = "renesas,r8a774c0-rpc-if",

--- 342 unchanged lines hidden --- 		1657 max-frequency = <200000000>;
1658 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1659 resets = <&cpg 311>;
1660 status = "disabled";
1661 };
1662
1663 rpc: spi@ee200000 {
1664 compatible = "renesas,r8a774c0-rpc-if",

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