r8a774c0.dtsi (9ddb236f13594b34a12dacf69a5adca7a1aef35e) r8a774c0.dtsi (a2053990f3275e715d69c208d8c0040cac0df593)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

--- 242 unchanged lines hidden (view full) ---

251 gpio-ranges = <&pfc 0 192 18>;
252 #interrupt-cells = <2>;
253 interrupt-controller;
254 clocks = <&cpg CPG_MOD 906>;
255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
256 resets = <&cpg 906>;
257 };
258
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

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251 gpio-ranges = <&pfc 0 192 18>;
252 #interrupt-cells = <2>;
253 interrupt-controller;
254 clocks = <&cpg CPG_MOD 906>;
255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
256 resets = <&cpg 906>;
257 };
258
259 pfc: pin-controller@e6060000 {
259 pfc: pinctrl@e6060000 {
260 compatible = "renesas,pfc-r8a774c0";
261 reg = <0 0xe6060000 0 0x508>;
262 };
263
264 cmt0: timer@e60f0000 {
265 compatible = "renesas,r8a774c0-cmt0",
266 "renesas,rcar-gen3-cmt0";
267 reg = <0 0xe60f0000 0 0x1004>;

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1693 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1695 clock-names = "pcie", "pcie_bus";
1696 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1697 resets = <&cpg 319>;
1698 status = "disabled";
1699 };
1700
260 compatible = "renesas,pfc-r8a774c0";
261 reg = <0 0xe6060000 0 0x508>;
262 };
263
264 cmt0: timer@e60f0000 {
265 compatible = "renesas,r8a774c0-cmt0",
266 "renesas,rcar-gen3-cmt0";
267 reg = <0 0xe60f0000 0 0x1004>;

--- 1425 unchanged lines hidden (view full) ---

1693 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1695 clock-names = "pcie", "pcie_bus";
1696 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1697 resets = <&cpg 319>;
1698 status = "disabled";
1699 };
1700
1701 pciec0_ep: pcie-ep@fe000000 {
1702 compatible = "renesas,r8a774c0-pcie-ep",
1703 "renesas,rcar-gen3-pcie-ep";
1704 reg = <0x0 0xfe000000 0 0x80000>,
1705 <0x0 0xfe100000 0 0x100000>,
1706 <0x0 0xfe200000 0 0x200000>,
1707 <0x0 0x30000000 0 0x8000000>,
1708 <0x0 0x38000000 0 0x8000000>;
1709 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1710 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1713 clocks = <&cpg CPG_MOD 319>;
1714 clock-names = "pcie";
1715 resets = <&cpg 319>;
1716 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1717 status = "disabled";
1718 };
1719
1701 vspb0: vsp@fe960000 {
1702 compatible = "renesas,vsp2";
1703 reg = <0 0xfe960000 0 0x8000>;
1704 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1705 clocks = <&cpg CPG_MOD 626>;
1706 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1707 resets = <&cpg 626>;
1708 renesas,fcp = <&fcpvb0>;

--- 252 unchanged lines hidden --- 		1720 vspb0: vsp@fe960000 {
1721 compatible = "renesas,vsp2";
1722 reg = <0 0xfe960000 0 0x8000>;
1723 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1724 clocks = <&cpg CPG_MOD 626>;
1725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1726 resets = <&cpg 626>;
1727 renesas,fcp = <&fcpvb0>;

--- 252 unchanged lines hidden ---