r8a774c0.dtsi (666fab4a3ea143315a9c059fad9f3a0f1365d54b) r8a774c0.dtsi (a5200e63af57d05ed8bf0ffd9a6ffefc40e01e89)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

--- 946 unchanged lines hidden (view full) ---

955 "ch12", "ch13", "ch14", "ch15",
956 "ch16", "ch17", "ch18", "ch19",
957 "ch20", "ch21", "ch22", "ch23",
958 "ch24";
959 clocks = <&cpg CPG_MOD 812>;
960 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
961 resets = <&cpg 812>;
962 phy-mode = "rgmii";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

--- 946 unchanged lines hidden (view full) ---

955 "ch12", "ch13", "ch14", "ch15",
956 "ch16", "ch17", "ch18", "ch19",
957 "ch20", "ch21", "ch22", "ch23",
958 "ch24";
959 clocks = <&cpg CPG_MOD 812>;
960 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
961 resets = <&cpg 812>;
962 phy-mode = "rgmii";
963 rx-internal-delay-ps = <0>;
963 iommus = <&ipmmu_ds0 16>;
964 #address-cells = <1>;
965 #size-cells = <0>;
966 status = "disabled";
967 };
968
969 can0: can@e6c30000 {
970 compatible = "renesas,can-r8a774c0",

--- 1008 unchanged lines hidden --- 		964 iommus = <&ipmmu_ds0 16>;
965 #address-cells = <1>;
966 #size-cells = <0>;
967 status = "disabled";
968 };
969
970 can0: can@e6c30000 {
971 compatible = "renesas,can-r8a774c0",

--- 1008 unchanged lines hidden ---