r8a774c0.dtsi (651a88798412e216f337d70181127e847f00a4b7) r8a774c0.dtsi (7ac8afba2257f08e95ef7d0e3ed2ac47cad9195b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

--- 131 unchanged lines hidden (view full) ---

140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 rwdt: watchdog@e6020000 {
145 compatible = "renesas,r8a774c0-wdt",
146 "renesas,rcar-gen3-wdt";
147 reg = <0 0xe6020000 0 0x0c>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

--- 131 unchanged lines hidden (view full) ---

140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 rwdt: watchdog@e6020000 {
145 compatible = "renesas,r8a774c0-wdt",
146 "renesas,rcar-gen3-wdt";
147 reg = <0 0xe6020000 0 0x0c>;
148 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cpg CPG_MOD 402>;
149 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
150 resets = <&cpg 402>;
151 status = "disabled";
152 };
153
154 gpio0: gpio@e6050000 {
155 compatible = "renesas,gpio-r8a774c0",

--- 1851 unchanged lines hidden --- 		149 clocks = <&cpg CPG_MOD 402>;
150 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
151 resets = <&cpg 402>;
152 status = "disabled";
153 };
154
155 gpio0: gpio@e6050000 {
156 compatible = "renesas,gpio-r8a774c0",

--- 1851 unchanged lines hidden ---