r8a774c0.dtsi (03abfdd31c66f0ecd629a1d1362e87551ce6c027) r8a774c0.dtsi (721b76195b31467e56851fbab3855e700f281270)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

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1805 };
1806 };
1807
1808 du: display@feb00000 {
1809 compatible = "renesas,du-r8a774c0";
1810 reg = <0 0xfeb00000 0 0x40000>;
1811 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

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1805 };
1806 };
1807
1808 du: display@feb00000 {
1809 compatible = "renesas,du-r8a774c0";
1810 reg = <0 0xfeb00000 0 0x40000>;
1811 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1813 clocks = <&cpg CPG_MOD 724>,
1814 <&cpg CPG_MOD 723>;
1813 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1815 clock-names = "du.0", "du.1";
1814 clock-names = "du.0", "du.1";
1815 resets = <&cpg 724>;
1816 reset-names = "du.0";
1816 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1817
1818 status = "disabled";
1819
1820 ports {
1821 #address-cells = <1>;
1822 #size-cells = <0>;
1823

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1818
1819 status = "disabled";
1820
1821 ports {
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1824

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