r8a774b1.dtsi (e700ac213a0f793fb4f83098413303e3dd080892) r8a774b1.dtsi (52e844ee9a6f460e6160736a43ef13317a91ca74)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774b1 SoC
4 *
5 * Copyright (C) 2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2128 status = "disabled";
2129 };
2130
2131 sdhi0: mmc@ee100000 {
2132 compatible = "renesas,sdhi-r8a774b1",
2133 "renesas,rcar-gen3-sdhi";
2134 reg = <0 0xee100000 0 0x2000>;
2135 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774b1 SoC
4 *
5 * Copyright (C) 2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2128 status = "disabled";
2129 };
2130
2131 sdhi0: mmc@ee100000 {
2132 compatible = "renesas,sdhi-r8a774b1",
2133 "renesas,rcar-gen3-sdhi";
2134 reg = <0 0xee100000 0 0x2000>;
2135 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2136 clocks = <&cpg CPG_MOD 314>;
2136 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
2137 clock-names = "core", "clkh";
2137 max-frequency = <200000000>;
2138 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2139 resets = <&cpg 314>;
2140 status = "disabled";
2141 };
2142
2143 sdhi1: mmc@ee120000 {
2144 compatible = "renesas,sdhi-r8a774b1",
2145 "renesas,rcar-gen3-sdhi";
2146 reg = <0 0xee120000 0 0x2000>;
2147 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2138 max-frequency = <200000000>;
2139 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2140 resets = <&cpg 314>;
2141 status = "disabled";
2142 };
2143
2144 sdhi1: mmc@ee120000 {
2145 compatible = "renesas,sdhi-r8a774b1",
2146 "renesas,rcar-gen3-sdhi";
2147 reg = <0 0xee120000 0 0x2000>;
2148 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2148 clocks = <&cpg CPG_MOD 313>;
2149 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
2150 clock-names = "core", "clkh";
2149 max-frequency = <200000000>;
2150 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2151 resets = <&cpg 313>;
2152 status = "disabled";
2153 };
2154
2155 sdhi2: mmc@ee140000 {
2156 compatible = "renesas,sdhi-r8a774b1",
2157 "renesas,rcar-gen3-sdhi";
2158 reg = <0 0xee140000 0 0x2000>;
2159 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2151 max-frequency = <200000000>;
2152 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2153 resets = <&cpg 313>;
2154 status = "disabled";
2155 };
2156
2157 sdhi2: mmc@ee140000 {
2158 compatible = "renesas,sdhi-r8a774b1",
2159 "renesas,rcar-gen3-sdhi";
2160 reg = <0 0xee140000 0 0x2000>;
2161 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2160 clocks = <&cpg CPG_MOD 312>;
2162 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
2163 clock-names = "core", "clkh";
2161 max-frequency = <200000000>;
2162 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2163 resets = <&cpg 312>;
2164 status = "disabled";
2165 };
2166
2167 sdhi3: mmc@ee160000 {
2168 compatible = "renesas,sdhi-r8a774b1",
2169 "renesas,rcar-gen3-sdhi";
2170 reg = <0 0xee160000 0 0x2000>;
2171 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2164 max-frequency = <200000000>;
2165 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2166 resets = <&cpg 312>;
2167 status = "disabled";
2168 };
2169
2170 sdhi3: mmc@ee160000 {
2171 compatible = "renesas,sdhi-r8a774b1",
2172 "renesas,rcar-gen3-sdhi";
2173 reg = <0 0xee160000 0 0x2000>;
2174 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2172 clocks = <&cpg CPG_MOD 311>;
2175 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
2176 clock-names = "core", "clkh";
2173 max-frequency = <200000000>;
2174 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2175 resets = <&cpg 311>;
2176 status = "disabled";
2177 };
2178
2179 rpc: spi@ee200000 {
2180 compatible = "renesas,r8a774b1-rpc-if",

--- 531 unchanged lines hidden --- 		2177 max-frequency = <200000000>;
2178 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2179 resets = <&cpg 311>;
2180 status = "disabled";
2181 };
2182
2183 rpc: spi@ee200000 {
2184 compatible = "renesas,r8a774b1-rpc-if",

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