r8a774a1.dtsi (eceb995e04b74204c73f9dd0ccb19061d5082063) r8a774a1.dtsi (391dca2105c435a2003c3c19f2d0b68742f43434)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1872 compatible = "renesas,fcpv";
1873 reg = <0 0xfe9af000 0 0x200>;
1874 clocks = <&cpg CPG_MOD 611>;
1875 power-domains = <&sysc R8A774A1_PD_A3VC>;
1876 resets = <&cpg 611>;
1877 iommus = <&ipmmu_vc0 19>;
1878 };
1879
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1872 compatible = "renesas,fcpv";
1873 reg = <0 0xfe9af000 0 0x200>;
1874 clocks = <&cpg CPG_MOD 611>;
1875 power-domains = <&sysc R8A774A1_PD_A3VC>;
1876 resets = <&cpg 611>;
1877 iommus = <&ipmmu_vc0 19>;
1878 };
1879
1880 vspb: vsp@fe960000 {
1881 compatible = "renesas,vsp2";
1882 reg = <0 0xfe960000 0 0x8000>;
1883 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1884 clocks = <&cpg CPG_MOD 626>;
1885 power-domains = <&sysc R8A774A1_PD_A3VC>;
1886 resets = <&cpg 626>;
1887
1888 renesas,fcp = <&fcpvb0>;
1889 };
1890
1891 vspd0: vsp@fea20000 {
1892 compatible = "renesas,vsp2";
1893 reg = <0 0xfea20000 0 0x5000>;
1894 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1895 clocks = <&cpg CPG_MOD 623>;
1896 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1897 resets = <&cpg 623>;
1898
1899 renesas,fcp = <&fcpvd0>;
1900 };
1901
1902 vspd1: vsp@fea28000 {
1903 compatible = "renesas,vsp2";
1904 reg = <0 0xfea28000 0 0x5000>;
1905 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1906 clocks = <&cpg CPG_MOD 622>;
1907 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1908 resets = <&cpg 622>;
1909
1910 renesas,fcp = <&fcpvd1>;
1911 };
1912
1913 vspd2: vsp@fea30000 {
1914 compatible = "renesas,vsp2";
1915 reg = <0 0xfea30000 0 0x5000>;
1916 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1917 clocks = <&cpg CPG_MOD 621>;
1918 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1919 resets = <&cpg 621>;
1920
1921 renesas,fcp = <&fcpvd2>;
1922 };
1923
1924 vspi0: vsp@fe9a0000 {
1925 compatible = "renesas,vsp2";
1926 reg = <0 0xfe9a0000 0 0x8000>;
1927 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1928 clocks = <&cpg CPG_MOD 631>;
1929 power-domains = <&sysc R8A774A1_PD_A3VC>;
1930 resets = <&cpg 631>;
1931
1932 renesas,fcp = <&fcpvi0>;
1933 };
1934
1880 csi20: csi2@fea80000 {
1881 compatible = "renesas,r8a774a1-csi2";
1882 reg = <0 0xfea80000 0 0x10000>;
1883 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1884 clocks = <&cpg CPG_MOD 714>;
1885 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1886 resets = <&cpg 714>;
1887 status = "disabled";

--- 175 unchanged lines hidden --- 		1935 csi20: csi2@fea80000 {
1936 compatible = "renesas,r8a774a1-csi2";
1937 reg = <0 0xfea80000 0 0x10000>;
1938 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MOD 714>;
1940 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1941 resets = <&cpg 714>;
1942 status = "disabled";

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