r8a774a1.dtsi (e700ac213a0f793fb4f83098413303e3dd080892) r8a774a1.dtsi (52e844ee9a6f460e6160736a43ef13317a91ca74)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2271 status = "disabled";
2272 };
2273
2274 sdhi0: mmc@ee100000 {
2275 compatible = "renesas,sdhi-r8a774a1",
2276 "renesas,rcar-gen3-sdhi";
2277 reg = <0 0xee100000 0 0x2000>;
2278 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2271 status = "disabled";
2272 };
2273
2274 sdhi0: mmc@ee100000 {
2275 compatible = "renesas,sdhi-r8a774a1",
2276 "renesas,rcar-gen3-sdhi";
2277 reg = <0 0xee100000 0 0x2000>;
2278 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2279 clocks = <&cpg CPG_MOD 314>;
2279 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
2280 clock-names = "core", "clkh";
2280 max-frequency = <200000000>;
2281 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2282 resets = <&cpg 314>;
2283 status = "disabled";
2284 };
2285
2286 sdhi1: mmc@ee120000 {
2287 compatible = "renesas,sdhi-r8a774a1",
2288 "renesas,rcar-gen3-sdhi";
2289 reg = <0 0xee120000 0 0x2000>;
2290 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2281 max-frequency = <200000000>;
2282 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2283 resets = <&cpg 314>;
2284 status = "disabled";
2285 };
2286
2287 sdhi1: mmc@ee120000 {
2288 compatible = "renesas,sdhi-r8a774a1",
2289 "renesas,rcar-gen3-sdhi";
2290 reg = <0 0xee120000 0 0x2000>;
2291 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2291 clocks = <&cpg CPG_MOD 313>;
2292 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
2293 clock-names = "core", "clkh";
2292 max-frequency = <200000000>;
2293 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2294 resets = <&cpg 313>;
2295 status = "disabled";
2296 };
2297
2298 sdhi2: mmc@ee140000 {
2299 compatible = "renesas,sdhi-r8a774a1",
2300 "renesas,rcar-gen3-sdhi";
2301 reg = <0 0xee140000 0 0x2000>;
2302 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2294 max-frequency = <200000000>;
2295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2296 resets = <&cpg 313>;
2297 status = "disabled";
2298 };
2299
2300 sdhi2: mmc@ee140000 {
2301 compatible = "renesas,sdhi-r8a774a1",
2302 "renesas,rcar-gen3-sdhi";
2303 reg = <0 0xee140000 0 0x2000>;
2304 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2303 clocks = <&cpg CPG_MOD 312>;
2305 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
2306 clock-names = "core", "clkh";
2304 max-frequency = <200000000>;
2305 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2306 resets = <&cpg 312>;
2307 status = "disabled";
2308 };
2309
2310 sdhi3: mmc@ee160000 {
2311 compatible = "renesas,sdhi-r8a774a1",
2312 "renesas,rcar-gen3-sdhi";
2313 reg = <0 0xee160000 0 0x2000>;
2314 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2307 max-frequency = <200000000>;
2308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2309 resets = <&cpg 312>;
2310 status = "disabled";
2311 };
2312
2313 sdhi3: mmc@ee160000 {
2314 compatible = "renesas,sdhi-r8a774a1",
2315 "renesas,rcar-gen3-sdhi";
2316 reg = <0 0xee160000 0 0x2000>;
2317 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2315 clocks = <&cpg CPG_MOD 311>;
2318 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
2319 clock-names = "core", "clkh";
2316 max-frequency = <200000000>;
2317 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2318 resets = <&cpg 311>;
2319 status = "disabled";
2320 };
2321
2322 rpc: spi@ee200000 {
2323 compatible = "renesas,r8a774a1-rpc-if",

--- 548 unchanged lines hidden --- 		2320 max-frequency = <200000000>;
2321 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2322 resets = <&cpg 311>;
2323 status = "disabled";
2324 };
2325
2326 rpc: spi@ee200000 {
2327 compatible = "renesas,r8a774a1-rpc-if",

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