r8a774a1.dtsi (e1076ce07b7736aed269c5d8154f2442970d9137) r8a774a1.dtsi (8811955d0a6d0abfa3e1c0cee30090fda0015069)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2312 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2313 clocks = <&cpg CPG_MOD 311>;
2314 max-frequency = <200000000>;
2315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2316 resets = <&cpg 311>;
2317 status = "disabled";
2318 };
2319
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2312 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2313 clocks = <&cpg CPG_MOD 311>;
2314 max-frequency = <200000000>;
2315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2316 resets = <&cpg 311>;
2317 status = "disabled";
2318 };
2319
2320 rpc: spi@ee200000 {
2321 compatible = "renesas,r8a774a1-rpc-if",
2322 "renesas,rcar-gen3-rpc-if";
2323 reg = <0 0xee200000 0 0x200>,
2324 <0 0x08000000 0 0x4000000>,
2325 <0 0xee208000 0 0x100>;
2326 reg-names = "regs", "dirmap", "wbuf";
2327 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2328 clocks = <&cpg CPG_MOD 917>;
2329 clock-names = "rpc";
2330 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2331 resets = <&cpg 917>;
2332 #address-cells = <1>;
2333 #size-cells = <0>;
2334 status = "disabled";
2335 };
2336
2320 gic: interrupt-controller@f1010000 {
2321 compatible = "arm,gic-400";
2322 #interrupt-cells = <3>;
2323 #address-cells = <0>;
2324 interrupt-controller;
2325 reg = <0x0 0xf1010000 0 0x1000>,
2326 <0x0 0xf1020000 0 0x20000>,
2327 <0x0 0xf1040000 0 0x20000>,

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2337 gic: interrupt-controller@f1010000 {
2338 compatible = "arm,gic-400";
2339 #interrupt-cells = <3>;
2340 #address-cells = <0>;
2341 interrupt-controller;
2342 reg = <0x0 0xf1010000 0 0x1000>,
2343 <0x0 0xf1020000 0 0x20000>,
2344 <0x0 0xf1040000 0 0x20000>,

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