r8a774a1.dtsi (9e35f49cf7037c3fe3fe4d51aec6d492741cddbe) r8a774a1.dtsi (8c965642354950cd17d1edff57fd5ca965040517)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2363 reg = <7>;
2364 remote-endpoint = <&vin7csi40>;
2365 };
2366 };
2367
2368 };
2369 };
2370
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2363 reg = <7>;
2364 remote-endpoint = <&vin7csi40>;
2365 };
2366 };
2367
2368 };
2369 };
2370
2371 hdmi0: hdmi@fead0000 {
2372 compatible = "renesas,r8a774a1-hdmi",
2373 "renesas,rcar-gen3-hdmi";
2374 reg = <0 0xfead0000 0 0x10000>;
2375 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2376 clocks = <&cpg CPG_MOD 729>,
2377 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2378 clock-names = "iahb", "isfr";
2379 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2380 resets = <&cpg 729>;
2381 status = "disabled";
2382
2383 ports {
2384 #address-cells = <1>;
2385 #size-cells = <0>;
2386 port@0 {
2387 reg = <0>;
2388 dw_hdmi0_in: endpoint {
2389 remote-endpoint = <&du_out_hdmi0>;
2390 };
2391 };
2392 port@1 {
2393 reg = <1>;
2394 };
2395 port@2 {
2396 /* HDMI sound */
2397 reg = <2>;
2398 };
2399 };
2400 };
2401
2371 du: display@feb00000 {
2372 compatible = "renesas,du-r8a774a1";
2373 reg = <0 0xfeb00000 0 0x70000>;
2374 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2375 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2376 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2377 clocks = <&cpg CPG_MOD 724>,
2378 <&cpg CPG_MOD 723>,

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2389 port@0 {
2390 reg = <0>;
2391 du_out_rgb: endpoint {
2392 };
2393 };
2394 port@1 {
2395 reg = <1>;
2396 du_out_hdmi0: endpoint {
2402 du: display@feb00000 {
2403 compatible = "renesas,du-r8a774a1";
2404 reg = <0 0xfeb00000 0 0x70000>;
2405 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2406 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2407 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2408 clocks = <&cpg CPG_MOD 724>,
2409 <&cpg CPG_MOD 723>,

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2420 port@0 {
2421 reg = <0>;
2422 du_out_rgb: endpoint {
2423 };
2424 };
2425 port@1 {
2426 reg = <1>;
2427 du_out_hdmi0: endpoint {
2428 remote-endpoint = <&dw_hdmi0_in>;
2397 };
2398 };
2399 port@2 {
2400 reg = <2>;
2401 du_out_lvds0: endpoint {
2402 remote-endpoint = <&lvds0_in>;
2403 };
2404 };

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2430 };
2431 port@2 {
2432 reg = <2>;
2433 du_out_lvds0: endpoint {
2434 remote-endpoint = <&lvds0_in>;
2435 };
2436 };

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