r8a774a1.dtsi (9ddb236f13594b34a12dacf69a5adca7a1aef35e) r8a774a1.dtsi (a2053990f3275e715d69c208d8c0040cac0df593)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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403 gpio-ranges = <&pfc 0 224 4>;
404 #interrupt-cells = <2>;
405 interrupt-controller;
406 clocks = <&cpg CPG_MOD 905>;
407 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
408 resets = <&cpg 905>;
409 };
410
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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403 gpio-ranges = <&pfc 0 224 4>;
404 #interrupt-cells = <2>;
405 interrupt-controller;
406 clocks = <&cpg CPG_MOD 905>;
407 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
408 resets = <&cpg 905>;
409 };
410
411 pfc: pin-controller@e6060000 {
411 pfc: pinctrl@e6060000 {
412 compatible = "renesas,pfc-r8a774a1";
413 reg = <0 0xe6060000 0 0x50c>;
414 };
415
416 cmt0: timer@e60f0000 {
417 compatible = "renesas,r8a774a1-cmt0",
418 "renesas,rcar-gen3-cmt0";
419 reg = <0 0xe60f0000 0 0x1004>;

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2366 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2367 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2368 clock-names = "pcie", "pcie_bus";
2369 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2370 resets = <&cpg 318>;
2371 status = "disabled";
2372 };
2373
412 compatible = "renesas,pfc-r8a774a1";
413 reg = <0 0xe6060000 0 0x50c>;
414 };
415
416 cmt0: timer@e60f0000 {
417 compatible = "renesas,r8a774a1-cmt0",
418 "renesas,rcar-gen3-cmt0";
419 reg = <0 0xe60f0000 0 0x1004>;

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2366 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2367 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2368 clock-names = "pcie", "pcie_bus";
2369 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2370 resets = <&cpg 318>;
2371 status = "disabled";
2372 };
2373
2374 pciec0_ep: pcie-ep@fe000000 {
2375 compatible = "renesas,r8a774a1-pcie-ep",
2376 "renesas,rcar-gen3-pcie-ep";
2377 reg = <0x0 0xfe000000 0 0x80000>,
2378 <0x0 0xfe100000 0 0x100000>,
2379 <0x0 0xfe200000 0 0x200000>,
2380 <0x0 0x30000000 0 0x8000000>,
2381 <0x0 0x38000000 0 0x8000000>;
2382 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2383 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2385 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2386 clocks = <&cpg CPG_MOD 319>;
2387 clock-names = "pcie";
2388 resets = <&cpg 319>;
2389 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2390 status = "disabled";
2391 };
2392
2393 pciec1_ep: pcie-ep@ee800000 {
2394 compatible = "renesas,r8a774a1-pcie-ep",
2395 "renesas,rcar-gen3-pcie-ep";
2396 reg = <0x0 0xee800000 0 0x80000>,
2397 <0x0 0xee900000 0 0x100000>,
2398 <0x0 0xeea00000 0 0x200000>,
2399 <0x0 0xc0000000 0 0x8000000>,
2400 <0x0 0xc8000000 0 0x8000000>;
2401 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2402 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2405 clocks = <&cpg CPG_MOD 318>;
2406 clock-names = "pcie";
2407 resets = <&cpg 318>;
2408 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2409 status = "disabled";
2410 };
2411
2374 fdp1@fe940000 {
2375 compatible = "renesas,fdp1";
2376 reg = <0 0xfe940000 0 0x2400>;
2377 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2378 clocks = <&cpg CPG_MOD 119>;
2379 power-domains = <&sysc R8A774A1_PD_A3VC>;
2380 resets = <&cpg 119>;
2381 renesas,fcp = <&fcpf0>;

--- 408 unchanged lines hidden --- 		2412 fdp1@fe940000 {
2413 compatible = "renesas,fdp1";
2414 reg = <0 0xfe940000 0 0x2400>;
2415 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2416 clocks = <&cpg CPG_MOD 119>;
2417 power-domains = <&sysc R8A774A1_PD_A3VC>;
2418 resets = <&cpg 119>;
2419 renesas,fcp = <&fcpf0>;

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