r8a774a1.dtsi (800037e815b91d8c9ad67906d18129e79a2cfcba) r8a774a1.dtsi (a5a41d50ffe77d250655f767eb192dbbc387edd7)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1909 interrupts = <GIC_PPI 9
1910 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1911 clocks = <&cpg CPG_MOD 408>;
1912 clock-names = "clk";
1913 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1914 resets = <&cpg 408>;
1915 };
1916
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1909 interrupts = <GIC_PPI 9
1910 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1911 clocks = <&cpg CPG_MOD 408>;
1912 clock-names = "clk";
1913 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1914 resets = <&cpg 408>;
1915 };
1916
1917 pciec0: pcie@fe000000 {
1918 compatible = "renesas,pcie-r8a774a1",
1919 "renesas,pcie-rcar-gen3";
1920 reg = <0 0xfe000000 0 0x80000>;
1921 #address-cells = <3>;
1922 #size-cells = <2>;
1923 bus-range = <0x00 0xff>;
1924 device_type = "pci";
1925 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1926 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1927 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1928 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1929 /* Map all possible DDR as inbound ranges */
1930 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1931 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1934 #interrupt-cells = <1>;
1935 interrupt-map-mask = <0 0 0 0>;
1936 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1937 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1938 clock-names = "pcie", "pcie_bus";
1939 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1940 resets = <&cpg 319>;
1941 status = "disabled";
1942 };
1943
1944 pciec1: pcie@ee800000 {
1945 compatible = "renesas,pcie-r8a774a1",
1946 "renesas,pcie-rcar-gen3";
1947 reg = <0 0xee800000 0 0x80000>;
1948 #address-cells = <3>;
1949 #size-cells = <2>;
1950 bus-range = <0x00 0xff>;
1951 device_type = "pci";
1952 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
1953 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
1954 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
1955 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
1956 /* Map all possible DDR as inbound ranges */
1957 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1958 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1961 #interrupt-cells = <1>;
1962 interrupt-map-mask = <0 0 0 0>;
1963 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1964 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
1965 clock-names = "pcie", "pcie_bus";
1966 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1967 resets = <&cpg 318>;
1968 status = "disabled";
1969 };
1970
1917 fdp1@fe940000 {
1918 compatible = "renesas,fdp1";
1919 reg = <0 0xfe940000 0 0x2400>;
1920 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1921 clocks = <&cpg CPG_MOD 119>;
1922 power-domains = <&sysc R8A774A1_PD_A3VC>;
1923 resets = <&cpg 119>;
1924 renesas,fcp = <&fcpf0>;

--- 355 unchanged lines hidden --- 		1971 fdp1@fe940000 {
1972 compatible = "renesas,fdp1";
1973 reg = <0 0xfe940000 0 0x2400>;
1974 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&cpg CPG_MOD 119>;
1976 power-domains = <&sysc R8A774A1_PD_A3VC>;
1977 resets = <&cpg 119>;
1978 renesas,fcp = <&fcpf0>;

--- 355 unchanged lines hidden ---