r8a774a1.dtsi (7b996955e514bd3639419c1e725bc3b69c96bd05) r8a774a1.dtsi (5f5249497bd7ed65d90cac36c3c3dabcda2903dd)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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132 compatible = "arm,cortex-a57";
133 reg = <0x0>;
134 device_type = "cpu";
135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci";
138 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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132 compatible = "arm,cortex-a57";
133 reg = <0x0>;
134 device_type = "cpu";
135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci";
138 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>;
140 capacity-dmips-mhz = <1024>;
140 };
141
142 a57_1: cpu@1 {
143 compatible = "arm,cortex-a57";
144 reg = <0x1>;
145 device_type = "cpu";
146 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci";
149 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
150 operating-points-v2 = <&cluster0_opp>;
141 };
142
143 a57_1: cpu@1 {
144 compatible = "arm,cortex-a57";
145 reg = <0x1>;
146 device_type = "cpu";
147 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
148 next-level-cache = <&L2_CA57>;
149 enable-method = "psci";
150 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>;
152 capacity-dmips-mhz = <1024>;
151 };
152
153 a53_0: cpu@100 {
154 compatible = "arm,cortex-a53";
155 reg = <0x100>;
156 device_type = "cpu";
157 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
158 next-level-cache = <&L2_CA53>;
159 enable-method = "psci";
160 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
161 operating-points-v2 = <&cluster1_opp>;
153 };
154
155 a53_0: cpu@100 {
156 compatible = "arm,cortex-a53";
157 reg = <0x100>;
158 device_type = "cpu";
159 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
160 next-level-cache = <&L2_CA53>;
161 enable-method = "psci";
162 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
163 operating-points-v2 = <&cluster1_opp>;
164 capacity-dmips-mhz = <560>;
162 };
163
164 a53_1: cpu@101 {
165 compatible = "arm,cortex-a53";
166 reg = <0x101>;
167 device_type = "cpu";
168 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
169 next-level-cache = <&L2_CA53>;
170 enable-method = "psci";
171 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
172 operating-points-v2 = <&cluster1_opp>;
165 };
166
167 a53_1: cpu@101 {
168 compatible = "arm,cortex-a53";
169 reg = <0x101>;
170 device_type = "cpu";
171 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
172 next-level-cache = <&L2_CA53>;
173 enable-method = "psci";
174 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
175 operating-points-v2 = <&cluster1_opp>;
176 capacity-dmips-mhz = <560>;
173 };
174
175 a53_2: cpu@102 {
176 compatible = "arm,cortex-a53";
177 reg = <0x102>;
178 device_type = "cpu";
179 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
180 next-level-cache = <&L2_CA53>;
181 enable-method = "psci";
182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
183 operating-points-v2 = <&cluster1_opp>;
177 };
178
179 a53_2: cpu@102 {
180 compatible = "arm,cortex-a53";
181 reg = <0x102>;
182 device_type = "cpu";
183 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
184 next-level-cache = <&L2_CA53>;
185 enable-method = "psci";
186 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
187 operating-points-v2 = <&cluster1_opp>;
188 capacity-dmips-mhz = <560>;
184 };
185
186 a53_3: cpu@103 {
187 compatible = "arm,cortex-a53";
188 reg = <0x103>;
189 device_type = "cpu";
190 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
194 operating-points-v2 = <&cluster1_opp>;
189 };
190
191 a53_3: cpu@103 {
192 compatible = "arm,cortex-a53";
193 reg = <0x103>;
194 device_type = "cpu";
195 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
196 next-level-cache = <&L2_CA53>;
197 enable-method = "psci";
198 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
199 operating-points-v2 = <&cluster1_opp>;
200 capacity-dmips-mhz = <560>;
195 };
196
197 L2_CA57: cache-controller-0 {
198 compatible = "cache";
199 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
200 cache-unified;
201 cache-level = <2>;
202 };

--- 2292 unchanged lines hidden --- 		201 };
202
203 L2_CA57: cache-controller-0 {
204 compatible = "cache";
205 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
206 cache-unified;
207 cache-level = <2>;
208 };

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