r8a774a1.dtsi (747bbcd3aacd95fe200cdda415dba02e872946b5) r8a774a1.dtsi (6af663af3c46300032fd7a783bdc3e585035438f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1174 };
1175
1176 canfd: can@e66c0000 {
1177 compatible = "renesas,r8a774a1-canfd",
1178 "renesas,rcar-gen3-canfd";
1179 reg = <0 0xe66c0000 0 0x8000>;
1180 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1174 };
1175
1176 canfd: can@e66c0000 {
1177 compatible = "renesas,r8a774a1-canfd",
1178 "renesas,rcar-gen3-canfd";
1179 reg = <0 0xe66c0000 0 0x8000>;
1180 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "ch_int", "g_int";
1182 clocks = <&cpg CPG_MOD 914>,
1183 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1184 <&can_clk>;
1185 clock-names = "fck", "canfd", "can_clk";
1186 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1187 assigned-clock-rates = <40000000>;
1188 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1189 resets = <&cpg 914>;

--- 1683 unchanged lines hidden --- 		1183 clocks = <&cpg CPG_MOD 914>,
1184 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1185 <&can_clk>;
1186 clock-names = "fck", "canfd", "can_clk";
1187 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1188 assigned-clock-rates = <40000000>;
1189 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1190 resets = <&cpg 914>;

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